Abstract: A vehicle radar system, apparatus and method use a radar control processing unit to generate a target response signal in at least a first dimension from compressed radar data signals and to perform cell-averaging constant false alarm rate (CA-CFAR) target detection by convolving the target response signal with a weighted kernel window signal in a frequency domain using a Fast Fourier Transform hardware accelerator, an element-wise multiplier, and an Inverse Fast Fourier Transform hardware accelerator to generate an output signal having a sign that indicates a target detection decision.

Abstract: A circuit includes a current mirror stage with a switch, that when made conductive, provides current between the input and the output of the current mirror stage through the switch. When the switch is nonconductive, current is not provided through the switch. The stage includes current mirror circuitry, that when the switch is nonconductive, provides current at the output that is mirrored from current provided to the input of the current mirror stage.

Abstract: A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (11-14, 17-20) which are separated from one another by a barrier oxide layer (15) and which are separately processed to form bottom gate electrodes having a first gate structure (40A-B) in the bottom Si/SiGe superlattice structures and to form top gate electrodes having a second, different gate structure (46A-B) in the top Si/SiGe superlattice structures.

Abstract: One example discloses a near-field communications device, including: a near-field antenna; a conformal material having a first surface and a second surface; wherein the first surface is dielectrically coupled to the antenna; and wherein the second surface is configured to be galvanically coupled to a host-structure.

Abstract: A processing system includes a system interconnect, a processor coupled to communicate with other components in the processing system through the system interconnect, distributed general purpose registers (GPRs) in the processing system wherein a first subset of the distributed GPRs is located in the processor and a second subset of the distributed GPRs is located in the processing system and external to the processor, and a first set of conductors directly connected between the processor and the second subsets of the distributed GPRs. An instruction execution pipeline in the processor accesses any register in the first and second subsets of the distributed GPRs as part of the processor's GPRs during instruction execution in the processor, in which the second subset of the distributed GPRs is accessed through the first conductor.

Abstract: Disclosed is a method of operating a low power wireless receiver in which a radio is periodically operable for receive intervals with sleep intervals therebetween and comprising a sleep clock having a sleep clock accuracy. A first transmission or packet is received. Based on a start moment of the first received packet, and an expected interval between packets, a nominal start moment is determined to start the radio for a packet window until a nominal end moment, for receiving a second packet; the packet window duration is extended in dependence on an estimated drift based on the SCA to provide a widened window. A start moment of a second received packet is measured within the widened window. An actual drift is calculated, from the start moment of the second packet; and an actual start moment and an actual window duration is determined, for receiving a third packet, based on the actual drift.

Abstract: In connection with an RF communication system, exemplary aspects involve a method for use in a communication system in which a first system (e.g., 802.11) that is asynchronously based and which is susceptible to interference from a second system (e.g., synchronous-based LTE-CV2X). Such interference is due to the frequency spectrum used by the first and second systems overlapping. To mitigate interference issues, example methods spreads out the times for messages in the first system, based on information concerning occupancy of the channel, and transmitting them relative to the end of a cycled transmission allocated for use by the second system.

Abstract: A package includes an integrated circuit, IC, die having circuitry configured to generate signalling for transmission to a waveguide and/or receive signalling from a waveguide via a launcher. The die is coupled to an interconnect layer extending out from a footprint of the die. The launcher is formed in a launcher-substrate, separate from the die. The launcher is coupled to the die to pass the signalling therebetween by a connection in the interconnect layer. The launcher includes a launcher element mounted in a first plane within the launcher-substrate and a waveguide-cavity including a ground plane arranged opposed to and spaced from the first plane. The waveguide-cavity is further defined by at least one side wall extending from the ground plane towards the first plane. The die and launcher are at least partially surrounded by mould material of the package.

Abstract: The disclosure relates to determining a carrier phase shift between a first transceiver and a second transceiver, each transceiver comprising a local oscillator for generating a carrier signal, an example method for which comprises: the first transceiver generating and transmitting a first continuous wave carrier signal packet; the second transceiver receiving the first continuous wave carrier signal packet; the second transceiver calculating a first phase correction based on a comparison between the received first continuous wave carrier signal packet and a local oscillator carrier signal at the second transceiver; the second transceiver generating and transmitting a second continuous wave carrier signal packet; the first transceiver receiving the second continuous wave carrier signal packet; the first transceiver calculating a second phase correction based on a comparison between the received second continuous wave carrier signal packet and a local oscillator signal at the first transceiver; and the first t

Abstract: Various embodiments relate to a detector circuit, including: a voltage source configured to produce a first voltage on a first output, a second voltage on a second output, and third voltage on a third output, wherein the first voltage is greater than the second voltage and the second voltage is greater than the third voltage; a first switch connected to the second output; a sampling capacitor connected to the switch, wherein the sampling capacitor is charged by the voltage source when the switch is closed; a first comparator with one input connected to the first output and a second input connected to the sampling capacitor; a second comparator with one input connected to the third output and a second input connected to the sampling capacitor; a multiplexer with a plurality of inputs configured to be connected to a plurality of terminals of an external circuit and an output connected to the sampling capacitor, the first input of the first comparator, and the first input of the second comparator; and a controll

Abstract: Disclosed is a method for designing an integrated circuit, wherein the integrated circuit is to be structured in cells, wherein the cells are to comprise functional cells and spare cells. The method comprises: a) designing at least one functional cell; and b) placing a plurality of functional cells on associated pattern positions of an, in particular regular, pattern matrix designed for the functional cells. The method further comprises c) placing, on at least one of the remaining pattern positions of the pattern matrix and instead of at least one spare cell conceivable for the at least one of the remaining pattern positions of the pattern matrix, a gate-based decoupling cell, and alternatively or in addition, d) placing, in at least one gap between pattern positions of the matrix pattern and instead of at least one filler cell conceivable for the at least one gap between pattern positions of the pattern matrix, a gate-based decoupling cell.

Abstract: A nanosheet semiconductor device and fabrication method are described for integrating the fabrication of nanosheet transistors (71) and capacitors/sensors (72) in a single nanosheet process flow by forming separate transistor and capacitor/sensor stacks (12A-16A, 12B-16B) which are selectively processed to form gate electrode structures (68A-C) which replace remnant SiGe sandwich layers in the transistor stack, to form silicon fixed electrodes using silicon nanosheets (13C, 15C) on a first side of the capacitor/sensor stack, and to form SiGe fixed electrodes using SiGe nanosheets (12C, 14C, 16C) from the middle of remnant SiGe sandwich layers in the capacitor/sensor stack (e.g., 16-2) which are separated from the silicon fixed electrodes by selectively removing top and bottom SiGe nanosheets (e.g., 16-1, 16-3) from the remnant SiGe sandwich layers in the capacitor/sensor stack.

Abstract: Various embodiments relate to a method and system for resuming a secure communication session with a server by a device, including: sending a message to the server requesting the resumption of a secure communication session; receiving from the server a server identifier, a server nonce, and a salt; determining that the device has a shared key with the server based upon the server identifier; determining that the received salt is valid; calculating a salted identifier based upon the shared key and the salt; sending the salted identifier to the server; and resuming the secure communication session with the server.

Abstract: In accordance with a first aspect of the present disclosure, a method is conceived for providing a digital representation of a transaction card in a mobile device, comprising: detecting, by a near field communication unit of said mobile device, that the transaction card is in proximity of the mobile device; upon or after said detecting, performing, by a processing unit of said mobile device, the following steps: retrieving the digital representation of the transaction card from a digitization server; loading the digital representation of the transaction card into a memory of the mobile device; activating the digital representation of the transaction card for a predefined validity period; invalidating the digital representation of the transaction card if no successful near field communication transaction has been performed within said validity period. In accordance with other aspects of the present disclosure, a corresponding computer program and a corresponding mobile device are provided.

Abstract: It is described a tamper detection device for detecting tampering with respect to a packaging, the device comprising: i) a first electrode comprising a first patterned structure, and ii) a second electrode comprising a second patterned structure. The first electrode and the second electrode are arranged so that the first patterned structure and the second patterned structure are at least partially opposite to each other. In a first arrangement state of the first patterned structure and the second patterned structure with respect to each other, a first capacitance is measurable, in a second arrangement state of the first patterned structure and the second patterned structure with respect to each other, a second capacitance is measurable, wherein the first capacitance is different from the second capacitance, and wherein the first arrangement state is different from the second arrangement state.

Abstract: There is described a method of determining a phase value for an NFC card emulating device that enables said NFC card emulating device to communicate in phase with an NFC reader device while utilizing active load modulation, wherein the NFC card emulating device comprises a card antenna and the NFC reader device comprises a reader antenna, the method comprising receiving a reader signal from the NFC reader device at the NFC card emulating device through coupling of the card antenna and the reader antenna, the reader signal comprising a subcarrier modulation; estimating a resonance frequency of a system corresponding to the coupled card antenna and reader antenna based on the received communication signal; and determining the phase value based on the estimated resonance frequency and a set of parameters that represents a predetermined reference system. Furthermore, an NFC card emulating device, an NFC system, and a computer program are described.

Abstract: A device for providing side-channel protection to a data processing circuit is provided and includes a chaotic oscillator and a counter. The data processing circuit has an input for receiving an input signal, a power supply terminal, and an output for providing an output signal. The chaotic oscillator circuit has an input coupled to receive a control signal, and an output coupled to provide an output signal for controlling a voltage level of a power supply voltage of the data processing circuit. The counter has an input coupled to receive a clock signal, and an output coupled to control a variable parameter of the chaotic oscillator in response to the clock signal. In another embodiment, a method is provided providing the side-channel protection to the device.

Abstract: The disclosure relates to a transceiver device, an electronic control unit and an associated method. The transceiver device is suitable for communicating between one or more network protocol controllers and a network bus and comprises: first interface circuitry configured to communicate with the one or more network protocol controllers; second interface circuitry configured to communicate with the one or more network protocol controllers; and selector circuitry configured to switch communication with the one or more network protocol controllers from the first interface circuitry to the second interface circuitry in response to a communication error in data carried on the first interface circuitry.

Abstract: A system, method, and apparatus are provided for handling communications with external communication channel hardware devices by a processor executing event-based programming code to interface a plurality of virtual machines with the external communication channel hardware devices by providing the processor with an event latch for storing hardware events received from the external communication channel hardware devices, with a timer circuit that generates a sequence of timer interrupt signals, and with a masking circuit that masks the hardware events stored in the event latch with an event mask in response to each timer interrupt signal, where each event mask is associated with a different virtual machine running on the processor such that each virtual machine is allowed to communicate only on a masked subset of the hardware events specified by the event mask to ensure freedom from interference between the plurality of virtual machines when communicating with the external communication channel hardware device

Abstract: A vehicle control device includes a plurality of IC units, while maintaining the operational reliability. The vehicle control device includes an IC unit for performing image processing on outputs from cameras; an IC unit for performing recognition processing of an external environment of the vehicle; and an IC unit for performing judgment processing for cruise control of the vehicle. A control flow is provided so as to allow the IC unit to transmit a control signal to the IC units and. The control flow is provided separately from a data flow configured to transmit the output from the cameras, the image data, and the external environment data.