Abstract: Provided is a method and system for switching between signals in an optical transport network. The method includes extracting identification data from an OTN signal at a termination sink and inserting the identification data into an Ethernet packet. The system includes a termination sink configured to extract identification data from an OTN signal and insert the identification data into an Ethernet packet.

Abstract: A method and apparatus are provided for de-multiplexing one or more Low-Order ODUj/ODUflex clients from a High-Order ODUk carrier. The number of TribSlots assigned to an ODUflex may be increased and decreased hitlessly, in accordance to ITU-T G.7044. In the Multiplexing direction, a Space-Time-Space switch is used to interleave bytes from Low-Order ODUk words into High-Order ODUk words. In the De-multiplexing direction, a similar switch is used to extract Low-Order ODUj bytes that are interleaved inside High-Order ODUk words and re-arrange them into Low-Order ODUj words.

Abstract: Provided is an apparatus and method for enabling interoperability between a serial attached small computer system interface (SAS) protocol with a peripheral component interconnect express (PCIe) protocol. A SAS-PCIe bridge includes a SAS component configured to communicate with a SAS device in a SAS domain and a PCIe component configured to communicate with a PCIe switch in a PCIe domain. The SAS component and the PCIe component are configured to convert data between the SAS protocol and the PCIe protocol.

Abstract: A system and method of delineating GFP data. The GFP framer comprises a candidate generator for generating an array of core header candidates from a data word received on a data bus, a candidate processor for generating a plurality of candidate tours and a frame delineator for identifying a candidate tour as an active tour and delineating the boundaries of the GFP frames defined by the active tour. Each core header candidate defines a reference position of one of the plurality of candidate tours. Each of the plurality of candidate tour comprises a record of core header positions for a series of GFP frames from the data word.

Abstract: The peak level of a high frequency analog signal in an RF receiver is detected by a system which samples the signal and compares it against a static threshold, generating an above/below status. The system is implemented with a sampler of sufficient aperture bandwidth to capture the signal in question, operated at a clock frequency, dynamically chosen as a function of fLO (local oscillator frequency) and the desired fIF (intermediate frequency), to minimize in-band intermodulation products. The sampler produces kickback intermodulation products that are positioned out-of-band, or are of low enough power in-band so as to be inconsequential. Samples are taken for a statistically significant period of time, and the status is used to adapt the threshold to systematically determine the peak amplitude of the signal being observed.

Abstract: A method and apparatus are disclosed for management of linked lists within a dynamic queue system. In a dynamic queue system where a central memory is shared amongst a set of queues, the method organizes the linked list structures of the queues. The linked list pointers of the queues are organized over a set of single port memories. Memory for the queue entries is allocated in an alternating fashion, which allows the method to provide per-cycle access to queues while reducing the footprint of the memory elements used for maintaining the linked list structures. The method disclosed reduces the overall memory requirements for the design and implementation of queue systems with multiple queues sharing a common pool of memory.

Abstract: A system for writing data to overlapping physical tracks of a shingled magnetic record (SMR) hard disk drive (HDD) and a method for creating a logical disk from overlapping physical tracks of the SMR HDD. The system comprises a write header and a memory identifying the overlapping physical tracks which are accessible through the logical disk. The physical tracks are spaced from each other by at least the width of the write header. The method comprises mapping in a memory the logical disk to writeable tracks of the overlapping physical tracks, the writeable tracks spaced from each other by at least the width of the write header.

Abstract: A storage controller includes data transfer logic defined to enable block level data transfer between the storage controller and multiple types of storage media within a storage volume. The storage controller also includes adaptive logic defined to determine in real-time which of the multiple types of storage media in the storage volume is to be used to store a given data block received by the storage controller. The received data block is stored on a determined storage medium in the storage volume. The data transfer logic and the adaptive logic are defined to maintain a normal interface between the storage controller and an operating system in communication with the storage controller, such that the multiple types of storage media in the storage volume is not apparent to the operating system.

Abstract: A controller comprising a transport layer, an internal memory, and a link list manager block. The internal memory stores pending instruction entries. The link list manager block is configured to read instructions stored in an external memory, update an active vector, the active vector for storing indications of instructions from the external memory; update the pending instruction entries in the internal memory; and update the instructions stored in the external memory. The link list manager block configured to dispatch a instruction from the pending instruction entries in the internal memory to the transport layer.

Abstract: A duty-cycle distortion self-correcting delay line has an even number of programmable delay lines connected in series between a data signal input and a data signal output. Each programmable delay line is paired with a corresponding inverting element. A data signal propagated from the input to the output is passed un-inverted in half of the delay lines and is passed inverted in the other half of the delay lines. When the data signal is a square wave clock signal, a duty cycle distortion caused by the delay lines passing the un-inverted signal is cancelled by a duty cycle distortion caused by the delay lines passing the inverted signal. The inverting elements may be XNOR or XOR gates connected to an anti-aging signal input which, when asserted, maintains all of the delay lines in order to avoid differential aging effects leading to acquired duty cycle distortion.

Abstract: A method and apparatus for powering up and powering down a laser diode and its driver are disclosed. The disclosed method and apparatus enable the use of deep sub-micron CMOS technology to build a laser diode driver (LDD), while ensuring the low voltage limits prescribed by such technology are not exceeded. Building an LDD with deep sub-micron CMOS technology pushes circuit integration further ahead, bringing cost of LDDs and required board circuits down.

Abstract: A nonvolatile memory storage controller for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes partitioning circuitry for identifying a set of soft-decision reference voltages having the smallest calculated introduced error value based upon the estimated BER of the nonvolatile memory. The controller further includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using the set of soft-decision reference voltages having the smallest calculated LLR introduced error value to provide a plurality of soft-decision bits representative of the codeword. The controller further includes an LLR look-up table accessible by the read circuitry to provide LLRs to the LDPC decoder for the subsequent decoding of the codeword.

Abstract: A random noise generation module for generating noisy LLRs for testing an error correction circuit of a nonvolatile memory storage module. The random noise generation module includes a coefficient generator for generating one or a plurality of coefficients, each of the plurality of coefficients associated with one region of a plurality of regions defining a linear space proportionately divided according to an area under a probability distribution curve for a nonvolatile memory storage module. The random noise generation module further includes a linear random number generator for generating a linear random number and a comparator for comparing the linear random number to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which the linear random number belongs to generate a noisy LLR for testing an error correction circuit of a nonvolatile memory storage module.

Abstract: A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.

Abstract: Provided is a method and apparatus for aligning a first local oscillator (LO) clock generated by a controllable LO clock generator in a first radio frequency (RF) path with a second LO clock in a second RF path. The apparatus includes a synchronization channel configured to exchange a synchronization clock between the first and second RF paths, a phase detector configured to measure a phase alignment between the first and second LO clocks, and a loop filter configured to drive the controllable LO clock generators using the phase alignment. Also provided is a time to digital converter. The time to digital converter includes a D flip-flop for sampling first and second input clocks with a third clock, and a counter configured to synchronously increment the resulting samples and create a digital proportional value representing the delay between the first and second clocks.

Abstract: A method is disclosed for setting or modifying a threshold voltage in a NAND flash memory, using an optimization method and based on an error, such as stored in a threshold voltage table. In an embodiment, a method is provided to optimize the read voltage on a NAND flash memory in order to minimize the errors on the NAND flash memory in the fewest reads operations as possible. Advantageously, the method of the present disclosure is more reliability as the method minimizes a Raw Bit Error Rate (RBER) on the NAND flash memory. In an embodiment, a NAND controller adjusts an existing cell read threshold voltage for a selected cell, using an iterative optimization method, based on a difference between first and second error rates, or a difference between first and second probabilities, to generate an adjusted cell read threshold voltage.

Abstract: A programmable passive peaking equalizer that can compensate for a frequency dependent loss of a variety of data channels is disclosed herein. Monotonic increase in signal loss vs. frequency of board traces, cables and even fiber causes significant distortion of transmitted data referred to as inter-symbol interference (ISI). Some embodiments of programmable passive equalizers disclosed herein can minimize ISI for a wide range of data channels with very low power penalty. Various embodiments of the passive equalizer can program the amount of peaking that occurs at the Nyquist frequency of the data rate, and hence compensates for high frequency signal loss. This in turn equalizes the high frequency patterns in the transmitted data stream, effectively eliminating the worst case ISI.

Abstract: A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.

Abstract: Provided is a method and apparatus for aligning a first local oscillator (LO) clock generated by a controllable LO clock generator in a first radio frequency (RF) path with a second LO clock in a second RF path. The apparatus includes a synchronization channel configured to exchange a synchronization clock between the first and second RF paths, a phase detector configured to measure a phase alignment between the first and second LO clocks, and a loop filter configured to drive the controllable LO clock generators using the phase alignment. Also provided is a time to digital converter. The time to digital converter includes a D flip-flop for sampling first and second input clocks with a third clock, and a counter configured to synchronously increment the resulting samples and create a digital proportional value representing the delay between the first and second clocks.

Abstract: A circuit and method for improving signal integrity characteristics of a non-full rate transmitter are disclosed herein. The circuit comprises an actuator block having an input for receiving a differential clock signal, the differential clock signal comprising a positive clock signal and a negative clock signal, the actuator configured to adjust a difference between the positive and negative clock signals; a sensing block, for sensing a difference between positive and negative signals of a differential signal, the differential signal being related to the clock signal; and a calibration block for providing a control signal to the actuator based on the sensed difference between the positive and negative signals.