Abstract: A circuit for reducing phase errors in a digital communication systems signal is provided. The circuit comprises a demodulator block, a feed-forward path, a feed-back path, and a slicer. The demodulator block generates a plurality of samples from the signal and determines for each sample a corresponding phase error. The feed-forward path is configured to reduce in the signal a high frequency component of the phase errors. The feed-back path configured to reduce in the signal a low frequency component of the phase errors. The slicer selectively forwards phase errors to the feed-forward path or the feed-back path based on a respective magnitude of the phase error when operating in a decision-directed mode.

Abstract: A low-density parity check (LDPC) decoder is provided for decoding low-density parity check (LDPC) encoded data wherein an adaptive check node approximation is performed at the check node processor utilizing the smallest magnitude log-likelihood ratio (LLR) and the second smallest magnitude log-likelihood ratio (LLR) to adapt to the current conditions at the check node.

Abstract: Methods and systems are provided for processing electrical signals derived from coherent dual polarization optical signals. A method comprises receiving first and second input signals, filtering the input signals by first and second complex SISO FIR to generate filtered input signals, filtering the filtered input signals and the input signals by first and second two-by-two matrix filters each having four branches to respectively generate equalized filtered signals and equalized signals, and, adapting the first and second complex SISO FIR filters based on the equalized signals and the equalized filtered signals.

Abstract: SAS/SATA Store-Forward (SSSF) buffering enables SAS/SATA block storage devices capable of slower physical link rates to transfer data at a SAS topology data rate. 6 Gbps SAS and SATA disk drives can exchange data at 12 Gbps with 12 Gbps hosts through 12 Gbps SAS expanders employing an SSSF device. The SSSF device improves data transfer performance in the storage area network by optimizing host-side link utilization. The device includes a host-side interface communicating with the host at a host-side rate, a drive-side interface communicating with the target at a drive-side rate equal to or less than the host-side rate, a buffer receiving SAS frames or SATA FIS's, and control logic to control communication between the host-side interface and buffer at the host-side rate and between the drive-side interface and the buffer at the drive-side rate.

Abstract: A system and method are disclosed for aggregated non-transparent requester ID translation in a PCIe switch. The system may include a first switch that is enabled to receive a request from a non-transparent port of a second switch at an aggregated downstream port of the first switch and translating the requester ID of the request at the first switch using the aggregated switch number and the captured bus number of the requester ID. The method may include receiving a request from a non-transparent port of a second switch at an aggregated downstream port of a first switch and translating the requester ID of the request at the first switch using the aggregated switch number and the captured bus number of the requester ID.

Abstract: An unrolled decision feedback equalizer (DFE) as disclosed herein has a reduced number of compensation factors while keeping a suitable performance level for a given application. The KN possible DFE correction levels are reduced or compressed into fewer levels (R), merging together the levels that are the closest together where K represents the number of possible symbols in each baud, or the number of bits encoded into each baud, and N represents the DFE depth in number of bauds. A mapping function is then provided to convert the KN combinations of previous history bits into R sampler selections.

Abstract: An equalization adaptation circuit comprises an equalizer, a transition determination circuit, a phase error circuit, a sequence recovery circuit, a phase error accumulator circuit, a transition accumulator circuit, and a controller circuit. The equalizer has adjustable parameters. The transition determination circuit determines observed transitions in an equalized signal output from the equalizer. A phase error circuit determines phase errors of the observed transitions. A sequence recovery circuit generates recovered digital data sequences. A phase error accumulator circuit accumulates the phase errors in respective association with pre-defined patterns matching the recovered digital data sequences containing observed transitions corresponding to the phase errors. A transition accumulator circuit accumulates a number of the observed transitions. A controller circuit controls the adjustable parameters of the equalizer based upon the accumulated phase errors and number of observed transitions.

Abstract: An equalizer is disclosed, and associated operational method. The equalizer has a configuration that balances performance and complexity by obtaining samples that are strongly correlated with future and past transmitted bits, and are weakly correlated with future and past bit transitions, and is useful for timing recovery circuits. Samples are only obtained or collected at time intervals more than one sample period away from the reference sample. Samples are shifted by a delay value less than the sample period, and are obtained at a sample period of one unit interval. A means to adjust the sampling point delay is also disclosed. In an implementation, samples that are within the sample period away from the reference sample are obtained and used for implementing a timing shift, not for equalization of the timing recovery signal. Embodiments are also disclosed for optimizing performance for data recovery.

Abstract: A system and a method for modulating an input signal are provided. The system includes a fractional-N phase locked loop (PLL) for frequency multiplying the input signal by a multiplication factor to generate an output signal. The fractional-N PLL includes an input signal path and a feedback signal path. The system includes a controllable delay line for inserting a linearizing tone into the input signal path or the feedback signal path of the fractional-N PLL.

Abstract: In a Ternary Content Addressable Memory (TCAM) optimized for network packet classification, network operation rules are preprocessed into sub-lists in accordance with a decision tree based packet classification algorithm. The decision tree is encoded as a lookup memory, which is accessed with a predetermined base address of higher order address bits combined with lower order address bits obtained from specific bit positions from a received network packet. Depending on the nodes traversed in the decision tree, different base addresses and values from different bit positions of the packet are used until a sub-list of potential rules is identified. A bitwise comparison of values of each rule against the packet is then executed, the matching rule with the highest precedence is returned as the matching table entry and the configured value associated with the entry is prepended to the packet.

Abstract: On-chip at-speed eye measurements of digitized signals in data and timing recovery circuits are disclosed. Eye diagrams and jitter measurements are used to evaluate signal quality and bath-tub Bit Error Rate characteristics in baseband communication systems. This disclosure describes a method and apparatus for digitally sampling a received signal at speed to produce an eye diagram of the received signal. This involves adding a small amount of circuitry to the existing prior art systems that use an interpolator for timing recovery and data recovery. In the present disclosure a temporary offset is applied to the interpolation index of the interpolator to obtain interpolated samples between the baud center and baud edge. The eye diagram can be produced from the received digitized and interpolated signal before equalization, or alternatively from the equalized signal.

Abstract: Methods and systems are provided for controlling elements in a signal path of a communication network to accommodate changes in the rate of a client signal. In particular, during the bandwidth resizing (BWR) portion of ITU-T Recommendation G.7044 Hitless Adjustment of ODUflex(GFP) protocol (HAO), the nodes in the chain along the ODUflex(GFP) signal path change their output rates in parallel such that FIFO over/underflow is avoided in the nodes. Certain embodiments provide mechanisms to synchronize and stabilize the nodes in a verifiable manner.

Abstract: A method of communicating count value information in an Optical Transport Network (OTN) signal frame. The method comprises determining a count value indicating a number of payload bytes to be sent in a next OTN signal frame; determining that a change in the count value (?) with respect to a current count value is within a predetermined range; selecting an inversion pattern indicating the change in the count value; determining a cyclic redundancy check (CRC) code associated with the inversion pattern; and, inserting the inversion pattern and the CRC code in a Generic Mapping Procedure (GMP) overhead of the OTN signal frame.

Abstract: In one embodiment, a method to boot up a server using a target storage device over a network is provided. In this embodiment, the method includes installing an operating system onto a server by storing the operating system in the target storage device located on the network. The location of the target device is designated by an internet protocol (IP) address. The method also includes using data block transfers in conjunction with the IP address to access the operating system on the target storage device.

Abstract: A method of reducing current leakage in unused circuits performed during semiconductor fabrication and a semiconductor device or integrated circuit thereby formed. The method involves modifying a characteristic of at least one idle circuit that is unused in a product variant, to inhibit the circuit and reduce current leakage therefrom upon powering as well as during operation. The method can substantially increase the Vt (threshold voltage) of all transistors of a given type, such as all N-type transistors or all P-type transistors. The method is also suitable for controlling other transistor parameters, such as transistor channel length, as well as other active elements, such as N-type resistors or P-type resistors, in unused circuits which affect leakage current as well as for other unused circuits, such as a high Vt circuit, a standard Vt circuit, a low Vt circuit, and an SRAM cell Vt circuit.

Abstract: Various embodiments of the invention provide resource management of available data bandwidth of a SAS system in a non-uniform way. In certain embodiments, arbitration wait time values are adaptively modified to achieve a specified performance quota for a link.

Abstract: A system and method reading, accumulating and processing soft information for use in LDPC decoding. In accordance with the present invention, an LDPC decoder includes accumulation circuitry to receive soft reads of a cell of the nonvolatile memory storage module and to produce an accumulated soft read that can be used to identify an appropriate LLR for the cell. The accumulation circuitry of the present invention may include, an accumulation RAM, an arithmetic logic unit (ALU) and a soft accumulation control and sequencing module for accumulating and processing soft information for use in LDPC decoding.

Abstract: A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of neighboring cell contribution LLR look-up tables representative of the contribution of the neighboring cells to threshold voltage distribution of the memory storage module. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword.

Abstract: A nonvolatile memory storage controller for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes partitioning circuitry for identifying a set of soft-decision reference voltages having the smallest calculated introduced error value based upon the estimated BER of the nonvolatile memory. The controller further includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using the set of soft-decision reference voltages having the smallest calculated LLR introduced error value to provide a plurality of soft-decision bits representative of the codeword. The controller further includes an LLR look-up table accessible by the read circuitry to provide LLRs to the LDPC decoder for the subsequent decoding of the codeword.

Abstract: A random noise generation module for generating noisy LLRs for testing an error correction circuit of a nonvolatile memory storage module. The random noise generation module includes a coefficient generator for generating one or a plurality of coefficients, each of the plurality of coefficients associated with one region of a plurality of regions defining a linear space proportionately divided according to an area under a probability distribution curve for a nonvolatile memory storage module. The random noise generation module further includes a linear random number generator for generating a linear random number and a comparator for comparing the linear random number to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which the linear random number belongs to generate a noisy LLR for testing an error correction circuit of a nonvolatile memory storage module.