Abstract: The present disclosure relates to a calibration circuit for an analog-to-digital converter (ADC). The calibration circuit includes a digital-to-analog converter (DAC) configured to generate a calibration voltage from a digital input, and a DC feedback control circuit. The DC feedback control circuit includes an ADC driver configured to operate in both an ADC calibration mode and in an ADC operation mode such that dynamic parameters of the ADC driver are unchanged when the ADC driver is operating in the ADC calibration mode and when the ADC driver is operating in the ADC operation mode. The DC feedback control circuit is also configured to: receive the calibration voltage from the DAC; modify the calibration voltage by cancelling offsets in the calibration voltage; and provide the modified calibration voltage to the ADC.

Abstract: A method and apparatus for controlling the effective gain of an ADC when the ADC is occasionally or continuously calibrated using the statistics of the input signal and when the statistics are not stationary.

Abstract: A method of background calibration of aperture center errors in a data communication system is provided. In an implementation, in response to detection of a low sampler output (“0”) in between two high sampler outputs (“1”), the method includes: calculating a signal derivative of an ADC output signal at the time of the detected low output; and adjusting timing at a selected sampler based on the calculated signal derivative. In an example implementation, the method includes watching for bubbles in the thermometer code output, and estimating the first derivative of the signal at the time of the bubble, then estimating the sign of the errors. In an example implementation, the errors are used in a control loop to reduce the aperture center error.

Abstract: Methods of protecting cache data are provided. For example, various methods are described that assist in handling dirty write data cached in memory by duplication into other locations to protect against data loss. One method includes caching a data item from a data source in a first cache device. The data item cached in the first cache device is designated with a first designation. In response to the data item being modified by a data consumer, the designation of the data item in the first cache device is re-assigned from the first designation to a second designation, and the data item with the second designation is copied to a second cache device.

Abstract: A method and apparatus, such as multi-engine controller that can be used to control multiple data processing engines in a command based IO processing system, such as a storage controller, to solve to the problem of scaling the data processing rate to match the advances in the IO interface data rates, including a method of identifying dependencies among various tasks queued up in the system and scheduling tasks out-of-order to avoid head of line blocking, a method to buffer and reorder the completed tasks such that the task output order is the same as that in the input to the system.

Abstract: A method and apparatus to independently adjust the output rise and fall time of a transmitter for the purposes of improving high-speed signaling characteristics and reducing electromagnetic interference (EMI). Also described is an apparatus to provide a high-speed edge-rate control feature. The disclosed method and apparatus for rise and fall time equalization has a closed-loop calibration system that includes an actuation apparatus within the transmitter driver, a sensing means at the output of the transmitter to measure the degree of rise/fall time imbalance, and a calibration state machine operating on the sensor output to devise correction control inputs to the actuator in the transmitter driver to correct the rise/fall time imbalance. Also described is how the actuation apparatus within the transmitter driver can further be used to provide an open-loop edge-rate control feature for the transmitter.

Abstract: A method of background calibration of threshold errors in a data communication system is provided. In an implementation, the method uses sampler statistics just after foreground calibration as the reference signal in a control loop method to remove individual sampler offsets. In an implementation in which an analog to digital converter (ADC) includes a plurality of sub-ADCs, gain, offset, and individual threshold errors across parallel, time-interleaved sub-ADCs are minimized by establishing individual comparator statistics for the average sub-ADC after an initial foreground calibration, then forcing each individual comparator to maintain its statistics over time, in the background, by continuously adjusting its threshold.

Abstract: A method and apparatus for interleaving high-speed, delta-sigma based over-sampled DACs. A delta-sigma modulator is decomposed into a parallel poly-phase block-filter running at a lower rate. The generated parallel digital data is then fed directly to the analog DAC output stage where it is directly combined to form the full-rate signal using a 1-hot-of-N output stage. By using a poly-phase implementation, the complexity of the high-speed parallel digital-analog timing interface is simplified, along with the timing requirements of the delta-sigma modulator which normally would have to run at the full-oversampled rate. The 1-hot-of-N signal encoding is directly generated from the parallel delta-sigma modulator, and efficiently encodes the data in such a way to minimize signal-dependent supply noise. The architecture disclosed is advantageous for the practical implementation of high-speed over-sampled DACs, such as those used in stringent wireless applications.

Abstract: A method of chaining a plurality of engines for a system on chip (SOC) controller device and a SOC controller device are disclosed herein. The method comprises: generating, at an initiator, a super-descriptor for providing instructions to the plurality of engines of the SOC controller; passing the super-descriptor from the initiator to a first engine of the plurality of engines; and executing a portion of the super-descriptor at each of the plurality of engines in series without the intervention of the initiator.

Abstract: An unrolled decision feedback equalizer (DFE) as disclosed herein has a reduced number of compensation factors while keeping a suitable performance level for a given application. The KN possible DFE correction levels are reduced or compressed into fewer levels (R), merging together the levels that are the closest together where K represents the number of possible symbols in each baud, or the number of bits encoded into each baud, and N represents the DFE depth in number of bauds. A mapping function is then provided to convert the KN combinations of previous history bits into R sampler selections.

Abstract: An unrolled decision feedback equalizer (DFE) as disclosed herein has a reduced number of compensation factors while keeping a suitable performance level for a given application. The KN possible DFE correction levels are reduced or compressed into fewer levels (R), merging together the levels that are the closest together where K represents the number of possible symbols in each baud, or the number of bits encoded into each baud, and N represents the DFE depth in number of bauds. A mapping function is then provided to convert the KN combinations of previous history bits into R sampler selections.

Abstract: A nonvolatile memory controller generates an error correction code for each data unit in a data stripe and generates a parity unit based on the data units of the data stripe. If a data unit of the data stripe has a number of data bit errors not exceeding the error correction capacity of the nonvolatile memory controller, the nonvolatile memory controller corrects any data bit errors in the data unit based on the error correction code of the data unit. Otherwise, if a data unit of the data stripe has a number of data bit error exceeding the error correction capacity of the nonvolatile memory controller, the nonvolatile memory controller recovers the data unit based on the other data units of the data stripe and the parity unit.

Abstract: This invention discloses circuit and methods to decouple and pipeline block decision feedback multiplexer (MUX) loop in parallel processing decision feedback circuits. In one embodiment of this invention, a block decision feedback MUX loop consists of a pipelined intra-block decision feedback MUX stage and an inter-block decision feedback MUX stage to handle intra-block decision feedback selection and inter-block decision feedback selection separately. In the pipelined intra-block decision feedback stage, inter-block dependency is eliminated to enable pipelining. In another embodiment of this invention for moderately timing-critical parallel processing decision feedback circuits, a block decision feedback MUX loop is piecewise split into multiple series connected segments that each segment contains parallel branches. The intra-segment decision feedback selections of different segments are decoupled and processed in parallel.

Abstract: An integer-N phase-locked loop based clock generator for generating an output clock signal with a frequency N multiples of a reference clock signal, and a method for same, wherein N is a positive integer. The integer-N clock phase-locked loop based generator comprises a reference clock, a voltage controlled oscillator, a clock divider, a first and second phase generator for generating a plurality of phases of the reference clock signal and divided down output clock signal, a plurality of phase frequency detectors and charge pumps. The method comprises generating a reference clock and an output clock signals, generating a plurality of phases of a divided down output clock signal and reference clock signal, comparing the plurality of phases, and changing the frequency of the output clock signal based on the comparison.

Abstract: A data storage device reads a data unit from a memory page, detects a number of data bit errors in the data unit, and generates a bit error indicator identifying bit indexes of the data bit errors in the data unit. The data storage device reads the data unit from the memory page once again and generates a corrected data unit by correcting data bit errors in the data unit based on the error correction code if the number of data bit errors in the data unit does not exceed an error correction capacity of the error correction code. Otherwise, the data storage device generates a modified data unit based on the data unit by negating at least one erroneous data bit the data unit based on the bit error indicator and corrects any remaining data bit errors in the modified data unit based on the error correction code.

Abstract: A data storage device stores a data unit in a memory page of a storage block along with an error correction code unit for the data unit. Additionally, the data storage device stores an error correction code unit for the data unit in a memory page of another storage block. In various embodiments, one or both of the error correction code units form an error correction code for correcting data bit errors in the data unit. Because the memory page containing the data unit does not have a storage capacity for simultaneously storing the error correction code and the data unit, the data storage device is capable of correcting a greater number of data bit errors in the data unit by using the error correction code in comparison to using an error correction code that would fit in the memory page.

Abstract: A method and apparatus, such as multi-engine controller that can be used to control multiple data processing engines in a command based IO processing system, such as a storage controller, to solve to the problem of scaling the data processing rate to match the advances in the IO interface data rates, including a method of identifying dependencies among various tasks queued up in the system and scheduling tasks out-of-order to avoid head of line blocking, a method to buffer and reorder the completed tasks such that the task output order is the same as that in the input to the system.

Abstract: Circuit and methods accelerate jitter tracking and reduce or eliminate the processing delay of loop filtering in timing recovery. A timing recovery circuit incorporates a phase tracking accelerator and a frequency tracking accelerator to compute the phase and frequency variation of incoming signal during the delay period of a loop filter. In one embodiment, phase and frequency tracking accelerators are realized in direct forms. In another embodiment, pre-computed look-up tables are employed in phase and frequency tracking accelerators to ease timing closure and simplify accelerator circuit. The phase tracking accelerator and the frequency tracking accelerator together compensate the estimated phase at the output of a loop filter and eliminate the processing delay of loop filtering. The loop bandwidth and jitter tolerance of timing recovery are increased.

Abstract: A communication system includes a destination node containing a message buffer pointer input queue and a message queue memory. Moreover, the message queue memory includes message buffers. A source node of the communication system generates data packets and a message buffer pointer packet. A message network of the communication system routes the data packets and the message buffer pointer packet to the destination node. The destination node writes a data message in a message buffer of the message queue memory based on the data packets and enqueues the message buffer pointer into the message buffer pointer input queue. Further, the destination node dequeues the message buffer pointer from the message buffer pointer input queue and accesses the data message in the message buffer based on a message buffer pointer.

Abstract: A nonvolatile memory controller may recover encoded data using the outer error correction code of the encoded data if it is determined that a correction capacity of the outer error correction code is not exceeded. Alternatively, the nonvolatile memory controller may recover the encoded data using the inner error correction code of the encoded data followed by the outer error correction code of the encoded data if it is determined that the correction capacity of the outer error correction code is exceeded. Additionally, if it is determined that the correction capacity of the outer error correction code is exceed after recovering the data using the inner error correction code, the nonvolatile memory storage module may perform a redundant array of independent disks (RAID) operation to recover the data.