Abstract: A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.

Abstract: A method and apparatus for modulating a beam from a laser with an electro-absorption modulator, and determining the optical power of the beam by measuring a back current produced by the electro-absorption modulator. The apparatus comprises an electro-absorption modulator and a back current detector. The electro-absorption modulator receives an electronic digital signal from an electro-absorption driver. The electro-absorption modulator modulates the beam of the laser according to the electronic digital signal. While modulating the beam, the electro-absorption modulator produces a back current. This back current is proportional to the optical power of the beam. The back current detector measures the back current to determine the optical power of the beam.

Abstract: A method of decoding a primary codeword and a set of secondary codewords stored in a non-volatile memory (NVM), which includes reading, from the NVM, the primary codeword and all the secondary codewords and storing them in a second memory. The primary codeword is then read from the second memory and decoded, utilizing a soft-decision decoder, based on a log-likelihood ratio (LLR) vector. When the decoding of the primary codeword is unsuccessful: each secondary codeword of the set of secondary codewords is read from the second memory and decoded, utilizing a hard-decision decoder, to identify and correct errored data bits in the each secondary codeword and to determine a location of each errored data bit in the primary codeword. An adjusted LLR vector is generated by adjusting the LLR for each primary codeword data bit based on the determined locations of the errored data bits in the primary codeword.

Abstract: A system and method of decoding a Reed-Solomon code using a Reed-Solomon decoder comprising an erasure location selector, multiple syndrome formers and multiple Berlekamp-Massey decoders that share a single error correction unit, and means for selecting a Berlekamp-Massey decoder output as the input to the error correction unit. The method improves the bit error rate performance of the Reed-Solomon decoder compared to known hard-decision and soft-decision Reed-Solomon decoders. The Reed-Solomon decoder also provides hardware area and power savings over more complex Reed-Solomon decoders.

Abstract: A method is provided for selecting a transmit link in a bonding group. Traffic is distributed to the links based on a selection method. Typical selection methods for bonded links of the same type include round robin or weighted round robin. A method is disclosed including selecting from among bonded links of different types based on link priority or link-to-group backpressure, sometimes both, and in some cases also based on traffic class. Link priority is based on the reliability, or quality, of the link. Adding link priority, and optionally traffic class, into the selection method allows high priority traffic to be always transported over high quality links. Also, considering the link-to-group backpressure, such as based on congestion status of operational links, or active links, will help avoid link congestion. The method is relevant to Quality of Service (QoS) implementation in transportation systems used for mobile backhaul or carrier access networks.

Abstract: A receiver equalizer that provides improved jitter tolerance relative to common adaptation mechanisms and that also provides inter-symbol interference. Improved jitter tolerance is an important benefit for SERDES receivers as tolerance to Sinusoidal Jitter is an important performance metric specified in most industry standards.

Abstract: This disclosure provides methods and apparatus for processing differential signals having non-inverted and inverted signals. An example apparatus has first and second circuit arms, each arm connected to receive one of the input signals. Each arm has a post-cursor branch comprising a delay, an inverter and a series terminating resistance connected between the first input and a first circuit arm common node, and a main cursor branch comprising a buffer and a series terminating resistance connected between the first input and the first circuit arm common node. A first transformer has a primary winding connected between the first circuit arm common node and a first output and a secondary winding connected between an output of the buffer of the main cursor branch of the second arm and ground, with a capacitor and a resistor connected in series between the secondary winding and ground.

Abstract: Apparatuses and methods for correcting errors in data read from memory cells of an integrated circuit device includes an encoder. The encoder is configured from a single parity check matrix and the encoder is configured to be virtually adjustable by setting a number of bits in the encoder to zero. A decoder is configured from the single parity check matrix and the decoder is configured to be virtually adjustable by setting a log-likelihood ratio (LLR) for a number of bits in the decoder to a strong value. A code-rate that the encoder and decoder uses can be changed by adjusting the number of bits in the encoder that are set to zero and the number of bits in the decoder that are set to the strong LLR value.

Abstract: An apparatus comprising a scrambler having a plurality of scrambler inputs and 2N scrambler outputs, and a unary-weighted digital to analog converter (DAC) connected to scrambler to generate an analog output signal based on the 2N scrambler outputs. The scrambler has N unique scrambling stages arranged in order between the scrambler inputs and the scrambler outputs from a first scrambling stage to a last scrambling stage. Each of the N unique scrambling stages has a plurality of stage inputs and outputs, with the stage inputs of the first scrambling stage connected to the scrambler inputs, the stage outputs of each scrambling stage except the last scrambling stage connected to the stage inputs of a next scrambling stage, and the stage outputs of the last scrambling stage connected to the scrambler outputs.

Abstract: A distributed Analog Finite Impulse Response (AFIR) filter circuit with n physical taps provides an output equivalent to an AFIR filter circuit with 2n?1 taps by emulating n?1 taps. An impedance mismatch, with respect to the characteristic impedance of the input and output transmission lines, is imposed at the input and output terminals to take advantage of the resulting reflective signal paths, which emulate the additional taps. This implementation results in space-savings and power-savings for on-chip implementations of the circuit. Implementations disclosed herein are advantageous in telecommunication applications that rely heavily on copper/FR4 backplanes in serial data links.

Abstract: A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.

Abstract: A method of reducing current leakage in product variants of a semiconductor device, during the fabrication of the semiconductor device. The method involves using a semiconductor process technique for reducing current leakage in semiconductor product variants having unused circuits. A semiconductor device or integrated circuit fabricated by this method has reduced current leakage upon powering as well as during operation. The method involves semiconductor process technique that substantially increases the Vt (threshold voltage) of all transistors of a given type, such as all N-type transistors or all P-type transistors.

Abstract: Systems and methods for correcting errors in data read from memory cells include a memory controller, which includes an encoder, and a decoder. The memory controller is configured to adjust a correctable raw bit error rate limit to correct different bit error rates occurring in data read from the memory cells. The correctable raw bit error rate limit is adjusted by switching the decoding between hard-decision decoding and soft-decision decoding, wherein a number of soft bits allocated for message values can be changed during soft-decision decoding. The correctable raw bit error rate is adjusted by changing the code-rate within the memory system while making virtual adjustments to the same encoder and decoder.

Abstract: A method and system are disclosed which determine a frequency offset between a reference clock frequency of a receiver and a transmit clock frequency embedded in a received non-return to zero (NRZ) signal. A polarity of the frequency offset is determined based on a moving direction of a sampling clock edge relative to an edge of a signal eye of the received NRZ signal and a region of the signal eye containing the sampling clock edge. A magnitude of the frequency offset is determined based on a time taken by the sampling clock edge to sweep the signal eye.

Abstract: A device that performs Quantization Noise-Shaping and operates at high clock rates. The device can be implemented in parallel with large parallelization factors to produce extremely high throughput. The device has two feed-forward filters that can be implemented using standard parallel Digital Signal Processing techniques. The device can be used in various systems such as Digital-to-Analog Converter (DAC) system and Fractional-N frequency synthesis systems.

Abstract: The present disclosure provides methods and apparatus for dynamically adjusting the common mode voltage at the LC tank node and/or the power supply voltage of a VCO with an LC resonator in order to force oscillation start-up by temporarily increasing gain. Methods according to certain preferred embodiments may reduce power consumption and/or overcome threshold voltage limitations and/or increase frequency and frequency tuning range during normal (steady-state) operation.

Abstract: The present disclosure provides a means to adjust the relative location of output rising and falling transitions to reduce single-ended duty cycle distortion (DCD) effects in the output data stream originating from the transmitter data path. This serves to improve high-speed single-ended signal characteristics and reduce electromagnetic interference (EMI). Another feature enabled by embodiments of the present disclosure is polarity skew (also referred to as differential skew) reduction between transmitter outputs. In an embodiment, the disclosed method and apparatus for transmitter data path single-ended DCD correction describes a closed-loop calibration system including the actuation apparatus within the transmitter, a sensing block at the output of the transmitter to measure the amount of single-ended DCD, and a calibration block operating on the sensor output to devise correction control inputs to the actuator in the transmitter to correct the data path single-ended DCD present.

Abstract: An oscillator and method for generating a signal are provided. The oscillator comprises an electro-mechanical resonator and a reconfigurable oscillator driver. The reconfigurable oscillator driver starts the oscillator in single-ended mode to avoid latching and transitions the oscillator to differential mode in such a manner as to sustain oscillations therein. The reconfigurable oscillator driver comprises two back-to-back banks of inverters and an adjustable feedback resistor. In single-ended mode, one bank is disabled and the other bank is enabled. To transition to differential mode and improve the quality of the signal, the number of enabled inverters is equalized in both banks.

Abstract: A method and apparatus are provided for multiplexing one or more Low-Order (LO) ODUj/ODUflex clients into a High-Order (HO) ODUk in an Optical Transport Network (OTN). LO bytes are multiplexed in accordance with a tributary slot assignment for a selected LO ODUj of the HO ODUk stream using a permutation matrix. In an implementation, each byte on each ingress port of a W-port space-time-space switch is configurably assigned to an associated timeslot of an associated egress port, using time-division multiplexing. The number of TribSlots assigned to an ODUflex may be increased and decreased hitlessly. A Clos-like Space-Time-Space switch is used to interleave bytes from Low-Order ODUk words into High-Order ODUk words.

Abstract: This disclosure describes a method and apparatus for signaling the phase and frequency of OTN and Constant Bit Rate (CBR) clients in an OTN network. The principles discussed are applicable when multiple stages of OTN multiplexing and demultiplexing are utilized. They are also applicable for use with the Generic Mapping Procedure (GMP) and Asynchronous Mapping Procedure (AMP). A method to use the phase and frequency of an ODUk/ODUflex to adjust a local reference clock to enable the recovery of the phase and frequency of a CBR client demapped from the ODUk/ODUflex is described.