Abstract: A semiconductor device includes: a semiconductor element that includes an element main body having an element main surface facing one side in a thickness direction, and a first electrode arranged on the element main surface; a first insulating layer that is arranged over a peripheral edge portion of the first electrode and the element main surface and includes a first annular portion formed in an annular shape when viewed in the thickness direction; and a second insulating layer that is laminated on the first insulating layer, is made of a resin material, and includes a second annular portion overlapping with the first annular portion when viewed in the thickness direction.

Abstract: An electronic component includes an insulating layer, a low voltage conductor pattern formed inside the insulating layer, a high voltage conductor pattern formed inside the insulating layer such as to face the low voltage conductor pattern in an up/down direction, and a withstand voltage enhancement structure of conductive property formed inside the insulating layer and along the high voltage conductor pattern such as to protrude further outside than the low voltage conductor pattern in plan view.

Abstract: This nitride semiconductor device is provided with: a depletion type transistor which comprises a first gate terminal, a first source terminal and a first drain terminal; and an enhancement type transistor which comprises a second gate terminal, a second source terminal and a second drain terminal. The second drain terminal is connected to the first source terminal; and the second source terminal is connected to the first gate terminal. The depletion type transistor comprises: an electron transit layer which is configured from a nitride semiconductor that contains aluminum in the crystal composition; and an electron supply layer which is formed on the electron transit layer and is configured from a nitride semiconductor that contains a larger amount of aluminum in the composition than the electron transit layer.

Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; at least one second semiconductor layer of a second conductivity type formed in the first semiconductor layer to have an annular shape in plan view; an insulating layer formed on the first semiconductor layer; a first metal layer and a second metal layer formed on the insulating layer and spaced apart from each other; a second wiring layer provided in the insulating layer and configured to electrically connect an inner region of the first semiconductor layer surrounded by the at least one second semiconductor layer and the second metal layer; and a first wiring layer provided in the insulating layer and configured to electrically connect an outer region of the first semiconductor layer on the opposite side from the inner region with respect to the at least one second semiconductor layer and the first metal layer.

Abstract: A nitride semiconductor device 1 includes a conductive SiC substrate 2 that has a first surface 2a and a second surface 2b opposite thereto, a semi-insulating SiC layer 3 that is formed in at least a portion of a surface layer portion at the first surface 2a side of the conductive SiC substrate 2, and a nitride epitaxial layer 40 that is formed on the conductive SiC substrate 2 such as to cover the semi-insulating SiC layer 3.

Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.

Abstract: A semiconductor device 1 includes a base body 3 that includes a p type substrate 4 and an n type semiconductor layer 5 formed on the p type substrate 4 and includes an element region 2 having a transistor 40 with the n type semiconductor layer as a drain, a p type element isolation region 7 that is formed in a surface layer portion of the base body such as to demarcate the element region, and a conductive wiring 25 that is disposed on a peripheral edge portion of the element region and is electrically connected to the n type semiconductor layer. The transistor includes an n+ type drain contact region 14 that is formed in a surface layer portion of the n type semiconductor layer in the peripheral edge portion of the element region. The conductive wiring is disposed such as to cover at least a portion of an element termination region 30 between the n+ type drain contact region and the p type element isolation region.

Abstract: A semiconductor device includes: a semiconductor layer having a surface; a first region and a second region of a first conductivity type, which are spaced apart from each other in a first direction on the surface and extend in a second direction orthogonal to the first direction, when viewed from a thickness direction orthogonal to the surface; a channel region of a second conductivity type; a gate electrode arranged on the channel region via a gate insulating film; a plurality of drift regions of a first conductivity type and a plurality of column regions of the second conductivity type; a buffer region of the first conductivity type; and at least one collector region of the second conductivity type.

Abstract: A semiconductor device includes: a semiconductor layer; trenches that are formed in the semiconductor layer, extend in first direction, and are spaced apart from each other in second direction, the trenches including a first trench located at outermost side in the second direction, and a second trench adjacent to the first trench; an insulating layer formed on the semiconductor layer and within the trenches; a source electrode formed on the insulating layer; a first buried electrode buried in the first trench; a second buried electrode buried above the first buried electrode in the first trench via the insulating layer; and a contact electrode arranged between two adjacent trenches of the plurality of trenches and connecting the source electrode and the semiconductor layer, wherein the second buried electrode has an upper end in contact with the source electrode and a lower end located below a lower end of the contact electrode.

Abstract: The semiconductor device includes a chip which has a main surface, a diode region which is arranged in the main surface, trench structures which are formed in the main surface at an interval in the diode region, the trench structures each having an electrode structure including an upper electrode and a lower electrode which are embedded in a trench across an insulator in an up/down direction, and a diode which has a pn-junction portion that is formed in a surface layer portion of the main surface at a region between the trench structures.

Abstract: A semiconductor device is manufactured which includes a SiC epitaxial layer, a plurality of transistor cells that are formed in the SiC epitaxial layer and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode that faces a channel region of the transistor cells in which a channel is formed when the semiconductor device is in an ON state, a gate metal that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode while being physically separated from the gate electrode, and a built-in resistor that is made of polysilicon and that is disposed below the gate metal so as to electrically connect the gate metal and the gate electrode together.

Abstract: A semiconductor device includes a chip having a main surface, first potential regions formed in a surface layer portion of the main surface, the second at a distance from the first potential region; a first conductivity type drift region between the first and second potential regions in the surface layer portion; RESURF arrays each including first conductivity type RESURF regions in a surface layer portion of the drift region at a distance from each other in a first direction to expose part of the drift region from the main surface, each RESURF region having an impurity concentration exceeding that of the drift region, the RESURF arrays being at a distance from each other in a second direction intersecting the first direction; a field insulating film covering the drift region and the RESURF arrays on the main surface; and a field electrode on the field insulating film covering the RESURF arrays.

Abstract: Systems and methods for growth of silicon carbide over a layer comprising graphene and/or hexagonal boron nitride, and related articles, are generally described. In some embodiments, a SiC film is fabricated over a layer comprising graphene and/or hexagonal boron nitride, which in turn is disposed over a substrate. The layer and/or the substrate may be lattice-matched with the SiC film to reduce defect density in the SiC film. The fabricated SiC film may then be removed from the substrate via, for example, a stressor attached to the SiC film. In certain cases, the layer serves as a reusable platform for growing SiC films and also serves a release layer that allows fast, precise, and repeatable release at the layer surface.

Abstract: A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.

Abstract: A gate driver, which drives an N-channel type transistor connected between an application terminal of an input voltage and an application terminal of a switch voltage, includes a capacitor circuit connected between an application terminal of a boot voltage higher than the switch voltage by a voltage between both ends of the boot capacitor and the application terminal of the switch voltage, and a timing control circuit that charges an input gate capacitance of the transistor with the boot voltage after precharging the same with the input voltage during turn-on transition of the transistor, and decreases capacitance value of the capacitor circuit after the turn-on transition of the transistor.

Abstract: The power module semiconductor device (2) includes: an insulating substrate (10); a first pattern (10a) (D) disposed on the insulating substrate (10); a semiconductor chip (Q) disposed on the first pattern; a power terminal (ST, DT) and a signal terminal (CS, G, SS) electrically connected to the semiconductor chip; and a resin layer (12) configured to cover the semiconductor chip and the insulating substrate. The signal terminal is disposed so as to be extended in a vertical direction with respect to a main surface of the insulating substrate.

Abstract: Semiconductor device (A10) includes conductive substrate (20) and semiconductor element (40). The conductive substrate (20) has obverse surface (20A) facing in thickness direction (z) and reverse surface (20B) facing opposite from the obverse surface (20A). The semiconductor element (40) is electrically bonded to the obverse surface (20A). The conductive substrate (20) includes first base layer (211), second base layer (212) and metal layer (22). The first base layer (211) and second base layer (212) are made of graphite composed of stacked graphenes. The metal layer (22) is between the first base layer (211) and the second base layer (212). The graphenes of the first base layer (211) are stacked in first stacking direction perpendicular to the thickness direction (z). The graphenes of the second base layer (212) are stacked in second stacking direction perpendicular to the thickness direction (z) and crossing the first stacking direction.

Abstract: The present disclosure provides a nitride semiconductor element. The nitride semiconductor element includes a semiconductor substrate having a substrate upper surface and a substrate lower surface facing opposite to the substrate upper surface, and having an active region and a peripheral region. A nitride semiconductor layer is selectively formed in the active region at the substrate upper surface to form a transistor. A source electrode and a drain electrode are in contact with the nitride semiconductor layer. A gate electrode is disposed between the source electrode and the drain electrode. A first electrode is formed on the substrate lower surface and used to electrically connect to the source electrode. The nitride semiconductor element includes a bidirectional Zener diode formed in the peripheral region and electrically connected to the first electrode.

Abstract: A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, and a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, and in the cell portion, formed to be thinner than a part in the outer peripheral portion.

Abstract: The power module semiconductor device (2) includes: an insulating substrate (10); a first pattern (10a) (D) disposed on the insulating substrate (10); a semiconductor chip (Q) disposed on the first pattern; a power terminal (ST, DT) and a signal terminal (CS, G, SS) electrically connected to the semiconductor chip; and a resin layer (12) configured to cover the semiconductor chip and the insulating substrate. The signal terminal is disposed so as to be extended in a vertical direction with respect to a main surface of the insulating substrate.