Abstract: An insulating transformer includes an insulation layer, a transformer embedded in the insulation layer, and a capacitor. The transformer includes first and second coils. The first coil includes a first signal terminal and a first ground terminal. The second coil is separated from the first coil in a thickness direction of the insulation layer and includes a second signal terminal and a second ground terminal. The capacitor includes first and second capacitor electrodes. The first capacitor electrode is connected to the first ground terminal of the first coil. The second capacitor electrode is located between the first capacitor electrode and the second coil and connected to the second ground terminal of the second coil. The insulating transformer further includes a first insulation film located between the first coil and the first capacitor electrode, and a second insulation film located between the second coil and the second capacitor electrode.

Abstract: A nitride semiconductor device includes: an electron transport layer constituted by a nitride semiconductor; an electron supply layer formed on the electron transport layer and constituted by a nitride semiconductor that has a larger band gap than the electron transport layer; a gate layer formed on the electron supply layer and constituted by a nitride semiconductor that has a smaller band gap than the electron supply layer and includes an acceptor impurity; a gate electrode formed on the gate layer; and a drain electrode and a source electrode in contact with the electron supply layer. The acceptor impurity includes zinc and magnesium, and the concentration profile of the zinc in the thickness direction of the gate layer is different from the concentration profile of the magnesium in the thickness direction of the gate layer.

Abstract: A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.

Abstract: An isolator includes an insulation layer and a capacitor embedded in the insulation layer. The capacitor includes: a first electrode portion arranged in the insulation layer and connected to a first pad; a second electrode portion arranged in the insulation layer and connected to a second pad; and an intermediate electrode portion arranged in the insulation layer and not connected to the first electrode portion and the second electrode portion. The intermediate electrode portion includes a first intermediate layer, a second intermediate layer, and a connector connecting the first intermediate layer and the second intermediate layer. The capacitor is formed by coupling the first electrode portion and the second electrode portion through the intermediate electrode portion.

Abstract: A nitride semiconductor device includes an electron transit layer, an electron supply layer, a gate layer, a gate electrode, a passivation layer, a source electrode, and a drain electrode. The gate layer includes a ridge including an upper surface of the gate layer, a source-side extension smaller in thickness than the ridge, and a drain-side extension smaller in thickness than the ridge. The source-side extension includes a first step portion including an upper surface parallel to a bottom surface of the gate layer and a first intermediate portion connecting the first step portion to the ridge. The drain-side extension includes a second step portion including an upper surface parallel to the bottom surface of the gate layer and a second intermediate portion connecting the second step portion to the ridge. The first intermediate portion has a cross-sectional area that is greater than that of the second intermediate portion.

Abstract: A comparator circuit includes a first comparator configured to compare a voltage based on an input voltage with a first reference voltage, a charge/discharge portion configured to switch between charging and discharging of a capacitor based on an output of the first comparator, a second comparator configured to compare a voltage of the capacitor with a second reference voltage, and a control portion. The control portion is configured to, in a case where the voltage of the capacitor is larger than a predetermined value when the charge/discharge portion performs switching from the charging of the capacitor to the discharging thereof, supply a predetermined voltage instead of the voltage based on the input voltage to the first comparator until the voltage of the capacitor becomes smaller than the predetermined value so that the discharging of the capacitor is maintained by the charge/discharge portion.

Abstract: A power supply system of the present disclosure includes: a plurality of output terminals, configured to output an output voltage; a group setting circuit, configured to group the plurality of output terminals; an anomaly detection circuit, configured to detect anomaly; and a control circuit, configured to stop an output from the output terminals belonging to groups in which an anomaly is detected by the anomaly detection circuit, and maintain an output from the output terminals belonging to groups in which an anomaly is not detected by the anomaly detection circuit.

Abstract: The present invention provides a nitride semiconductor device, including an insulating substrate, a substrate over the first surface of the insulating substrate, a first lateral transistor over a first region of the substrate, wherein the first lateral transistor includes a first nitride semiconductor layer formed over the substrate, and a first gate electrode, a first source electrode and a first drain electrode formed over the first nitride semiconductor layer, and a second lateral transistor over a second region of the substrate, wherein the second lateral transistor includes a second nitride semiconductor layer formed over the substrate, and a second gate electrode, a second source electrode and a second drain electrode formed over the second nitride semiconductor layer, and a separation trench formed over a third region, wherein the third region is between the first region and the second region.

Abstract: A MEMS device includes a substrate which has a first main surface and a second main surface facing the first main surface, and in which a silicon substrate, a silicon carbide layer having conductivity, and a silicon layer are sequentially stacked from a second main surface side toward a first main surface side, a cavity recessed over the silicon layer, the silicon carbide layer, and the silicon substrate from the first main surface of the substrate to the second main surface side of the substrate, a MEMS electrode which is arranged in the cavity, is composed of the silicon layer and the silicon carbide layer, and is spaced apart from a bottom surface of the cavity to the first main surface side, and an isolation joint which divides the MEMS electrode in a plan view and mechanically connects and electrically isolates both sides of the divided MEMS electrode.

Abstract: This isolation transformer includes: an isolation layer; a transformer having a first coil and a second coil; and a capacitor having a first capacitor electrode and a second capacitor electrode disposed between the first coil and the second coil. The isolation layer includes a first isolation film in which the first coil is embedded, a second isolation film on the upper surface of the first isolation film, a protective film on the upper surface of the second isolation film, a third isolation film on the upper surface of the protective film, a fourth isolation film on the upper surface of the third isolation film, and a fifth isolation film on the upper surface of the fourth isolation film. The second capacitor electrode is formed between the third isolation film and the fourth isolation film. The second coil is formed between the fourth isolation film and the fifth isolation film.

Abstract: An isolation transformer includes an insulation layer, a transformer, and a capacitor. The transformer includes first and second coils separated from each other in a thickness-wise direction of the insulation layer. The capacitor includes a first capacitor electrode and a second capacitor electrode. The insulation layer includes thin films and interlayer insulation films alternately stacked in the direction. The thin films include first and second thin films separated from each other in the direction. The interlayer insulation films include a first interlayer insulation film located next to the first thin film in the direction and a second interlayer insulation film located next to the second thin film in the direction. The first capacitor electrode is formed between the first thin film and the first interlayer insulation film. The second capacitor electrode is formed between the second thin film and the second interlayer insulation film.

Abstract: An isolation transformer includes an insulation layer and a transformer. The transformer includes a first coil and a second coil embedded in the insulation layer. The first coil and the second coil are opposed to each other in a thickness-wise direction of the insulation layer. The first coil and the second coil include non-overlapping portions that do not overlap each other in the thickness-wise direction of the insulation layer.

Abstract: A nitride semiconductor device includes an electron transit layer, formed above a substrate, and an electron supply layer formed on the electron transit layer and having a larger band gap than the electron transit layer. A gate layer is formed on the electron supply layer and contains an acceptor impurity. A gate electrode is formed on the gate layer. A source electrode and a drain electrode are located at opposite sides of the gate layer and contact the electron supply layer. The gate electrode has a greater length than the gate layer in a first direction in which the source electrode, the gate layer, and the drain electrode are arranged. The gate electrode contacts an entire upper surface of the gate layer and extends from the gate layer toward at least one of the source electrode and the drain electrode.

Abstract: A switch device includes a switching element that connects/disconnects a current path from a power supply terminal to a ground terminal via a load, and an overcurrent protection circuit that limits output current flowing in the switching element to be an overcurrent limit value or less. When an output short circuit of the load is detected, the overcurrent protection circuit decreases the overcurrent limit value to be lower as a power supply voltage is higher. In addition, the switch device preferably includes a switching element that connects/disconnects a current path from a power supply terminal to a ground terminal via a load, an intermittent control unit that intermittently drives the switching element when an abnormality is detected, and an output voltage monitoring portion that disables the intermittent control unit until an output voltage applied to the load reaches its target value.

Abstract: A semiconductor device includes an oscillator configured to generate a first clock signal, a first terminal via which an input clock signal is fed in from the outside, a first counter configured to count a clock signal based on the first clock signal between edges in the input clock signal, and a controller configured to send to the oscillator an instruction to adjust the frequency of the first clock signal based on the result of comparison of the count value by the first counter with an expected value.

Abstract: A semiconductor structure for inspection includes a semiconductor plate having a first main surface on one side and a second main surface on the other side, an inspection region provided in the first main surface, a main surface electrode having a first hardness and covering the first main surface in the inspection region, and a protective electrode having a second hardness which exceeds the first hardness, covering the main surface electrode in the inspection region, and forming a current path between the second main surface and the protective electrode via the semiconductor plate.

Abstract: This semiconductor device comprises a peripheral region surrounding a cell region, a gate electrode disposed in the peripheral region, and an emitter electrode. The emitter electrode includes a cell electrode portion, a peripheral electrode portion formed at a distance from the cell electrode portion in the peripheral region, and a connecting portion connecting the cell electrode portion and the peripheral electrode portion. The peripheral region includes a well region formed to surround the cell region, an insulating film and an intermediate insulating film that cover the well region, and a gate finger embedded in the insulating films. The connecting portion is formed across the gate finger on the intermediate insulating film. The peripheral electrode portion is electrically connected to the well region.

Abstract: A semiconductor device comprises: a cell region and a peripheral region. The cell region includes an insulation film covering cells, and an electrode portion including a stacked part stacked on the insulation film. The peripheral region includes a first semiconductor layer of a first conductive type, a second semiconductor region of a second conductivity type, a peripheral insulation film, a peripheral electrode portion, a barrier layer, and a passivation film. The barrier layer covers both the peripheral insulation film and the peripheral electrode portion and has a smaller diffusion coefficient than the peripheral insulation film. The passivation film stacks on the barrier layer and has a larger diffusion coefficient than the barrier layer. The peripheral electrode portion includes a projection. A thickness of the projection is less than a thickness of the stacked part.