Abstract: Semiconductor wafers with improved geometry are produced from a workpiece by processing the workpiece by means of a wire saw, by feeding the workpiece through an arrangement of wires which are tensioned between wire guide rollers and move in a running direction; producing kerfs when the wires engage into the workpiece; determining a placement error of the kerfs; and inducing a compensating movement of the workpiece as a function of the determined placement error along a longitudinal axis of the workpiece during the feeding of the workpiece through the arrangement of wires.

Abstract: The invention relates to a method of processing a semiconductor in the semiconductor wafer is disposed on a susceptor in a coating apparatus and processed, wherein an etching gas is passed through the coating apparatus in an etching step. The invention further relates to a control system for controlling a coating apparatus for processing a semiconductor water, to a plant for processing a semiconductor wafer having a coating apparatus which comprises the control system, and a semiconductor wafer. A first side of the semiconductor wafer which has been subjected to a polishing operation by CMP, or a second side of the semiconductor wafer opposite the first side, is coated with a protective layer before processing.

Abstract: Semiconductor wafers are polished on both sides between polishing pads of a Shore A hardness of at least 80 and a compressibility of less than 3%, attached to upper and lower polishing plates, the polishing pads attached to the upper and lower polishing plates by bonding the polishing pads to the plates, and positioning an intermediate pad having a compressibility of at least 3% between the two bonded polishing pads as an intermediate layer and then pressing together the two polishing pads with the intermediate pad situated therebetween for a period of time.

Abstract: A separating apparatus for polysilicon has at least one screen plate, comprising a feed region for polysilicon, a profiled region having peaks and valleys, a region having screen apertures which adjoins the profiled region, and a takeoff region, wherein the screen apertures widen in the direction of the takeoff region, and a separating plate which is horizontally and vertically displaceable is arranged below the screen apertures.

Abstract: Semiconductor wafers, are processed using minimally three processing operations: a first double-sided polishing operation, a second chemical-mechanical polishing operation and an epitaxial coating operation. A control system for conducting the method defines at least one operating parameter for the processing operations specifically based on at least one wafer parameter measured on the semiconductor wafer after processing in at least one processing operation, based on an actual state of a processing apparatus with which the respective processing operation is conducted, and based on optimizing wafer parameters for flatness after the wafer has undergone all three processing operations instead of optimizing each individual processing step for optimal flatness.

Abstract: A method dresses one polishing cloth or two polishing pads simultaneously, in which a polishing cloth has been applied to a polishing plate, with at least one dresser (4), which is equipped with at least one dressing element (8), this at least one dressing element (8) being in contact with the at least one polishing cloth (11, 12) to be dressed, wherein the at least one polishing plate (21, 22) is rotated with a relative rotational speed and the at least one dresser (4) is rotated with a relative rotational speed and at least two different combinations of directions of rotation of the two pairs of polishing plates (21, 22) and pin wheels (31, 32) are executed during the simultaneous dressing of two polishing pads (11, 12) or during the dressing of one polishing cloth (11) of the polishing plate (21) and of the at least one dresser (4).

Abstract: A monocrystalline semiconductor wafers have an average roughness Ra of at most 0.8 nm at a limiting wavelength of 250 ?m, and an ESFQRavg of 8 nm or less given an edge exclusion of 1 mm. The wafers are advantageously produced by a method comprising the following steps in the indicated order: a) simultaneous double-side polishing of the semiconductor wafer, b) local material-removing processing of at least one part of at least one side of the semiconductor wafer using a fluid jet which contains suspended hard substance particles and which is directed onto a small region of the surface with the aid of a nozzle, wherein the nozzle is moved over that part of the surface which is to be treated in such a way that a predefined geometry parameter of the semiconductor wafer is improved, and c) polishing of the at least one surface of the semiconductor wafer.

Abstract: Single crystals of semiconductor material are produced by an FZ method, wherein a molten zone is created between a feed rod and a growing single crystal; the method involving melting feed rod material in a high frequency magnetic field of a first induction coil; crystallizing material of the molten zone on top of the growing single crystal; rotating the growing single crystal about an axis of rotation and changing the direction of rotation and the speed of rotation according to a predetermined pattern; and imposing an alternating magnetic field of a second induction coil on the molten zone, wherein the alternating magnetic field is not axisymmetric with respect to the axis of rotation of the growing single crystal.

Abstract: Polysilicon chunks or granules are classified into size fractions using a mechanical screen having a profiled surface having peaks and valleys, and terminating in widening slots through which a polysilicon size fraction falls. The device is effective and the slots are resistant to clogging.

Abstract: Single crystal semiconductor ingots are pulled from a melt contained in a crucible by a method of controlling the pulling the single crystal in a phase in which an initial cone of the single crystal is grown until a phase in which the pulling of a cylindrical section of the single crystal is begun, by measuring the diameter Dcr of the initial cone of the single crystal and calculating the change in the diameter dDcr/dt; pulling the initial cone of the single crystal from the melt at a pulling rate vp(t) from a point in time t1 until a point in time t2, starting from which the pulling of the cylindrical section of the single crystal in conjunction with a target diameter Dcrs is begun, wherein the profile of the pulling rate vp(t) from the point in time t1 until the point in time t2 during the pulling of the initial cone is predetermined by means of an iterative computation process.

Abstract: FZ single crystals are pulled by melting a polycrystal with electromagnetic melting apparatus and then recrystallizing. First, a lower end of the polycrystal is melted; second, a monocrystalline seed is attached to the lower end of the polycrystal and melted beginning from an upper end thereof; third, between a lower section of the seed and the polycrystal, a thin neck is formed whose diameter (dD) is smaller than that (dI) of the seed; and fourth, between the thin neck section and the polycrystal, a conical section is formed. Before the conical growth, a switchover position (h?) of the polycrystal, the position at which the rate of polycrystal movement relative to the melting apparatus is to be reduced is determined, and the rate is reduced, in amount when the switchover position (h?) is reached.

Abstract: A single crystal is pulled by an FZ method, in which a polycrystal is melted by means of an electromagnetic melting apparatus and then recrystallized, wherein a first phase (P1) a lower end of the polycrystal, which is moved toward the melting apparatus, is melted by the melting apparatus to form a drop, and in a second phase (P2) a monocrystalline seed is attached to the lower end of the polycrystal and is melted beginning from an upper end of the seed, where a power (P) of the melting apparatus during the first phase (P1) and during the second phase (P2) is predetermined at least temporarily in dependence on a temperature and/or geometrical dimensions of crystal material used which comprises the drop and/or the seed and/or the polycrystal.

Abstract: A susceptor for holding a semiconductor wafer with an orientation notch during deposition of a layer on the wafer comprises a susceptor ring having a placement area for placing the semiconductor wafer in the edge region of a back side of the semiconductor wafer and a step-shaped outer delimitation of the susceptor ring adjoining the placement area. The susceptor has four positions at which the structure differs from the structure at four further positions, the spacing from one of the four positions to the next of the four positions being 90°, the spacing from one of the four positions to the next further position being 45°, one of the four positions being a notch position at which the structure of the susceptor differs from the structure of the susceptor at the three other positions of the four positions of the susceptor.

Abstract: Coated semiconductor wafers are produced by introducing a process gas through first gas inlet openings along a first flow direction into a reactor chamber and over a substrate wafer of semiconductor material lying on a susceptor in order to deposit a layer on the substrate wafer, whereby material derived from the process gas precipitates on a preheat ring arranged around the susceptor; extracting the coated substrate wafer from the reactor chamber; and subsequently removing material precipitate from the preheat ring by introducing an etching gas through the first gas inlet openings into the reactor chamber along the first flow direction over the preheat ring and also through second gas inlet openings between which the first gas inlet openings are arranged, along further flow directions which intersect with the first flow direction.

Abstract: Semiconductor wafers are produced by a process wherein a single-crystal ingot of semiconductor material is pulled and at least one wafer is removed from the ingot, wherein the wafer is subjected to a thermal treatment comprising a heat treatment step in which a radial temperature gradient acts on the wafer, wherein an analysis of the wafer of semiconductor material with respect to the formation of defects in the crystal lattice, so-called stress fields, is carried out.

Abstract: Semiconductor wafers useful for NAND circuitry and having a front side, a rear side, a middle and a periphery, have an Nv region which extends from the middle to the periphery; a denuded zone which extends from the front side to a depth of not less than 20 ?m into the interior of the semiconductor wafer, where the density of vacancies in the denuded zone, determined by means of platinum diffusion and DLTS is not more than 1×1013 vacancies/cm3; a concentration of oxygen of not less than 4.5×1017 atoms/cm3 and not more than 5.5×1017 atoms/cm3; a region in the interior of the semiconductor wafer which adjoins the denuded zone and has nuclei which can be developed by means of a heat treatment into BMDs having a peak density of not less than 6.0×109/cm3, where the heat treatment comprises heating the semiconductor wafer to a temperature of 800° C. over a period of four hours and to a temperature of 1000° C. over a period of 16 hours. The wafers are produced by a unique RTA treatment of Nv wafers.

Abstract: Semiconductor wafers are coated with an epitaxially deposited layer in an epitaxy reactor, wherein at least one semiconductor wafer is arranged on a respective susceptor in the epitaxy reactor and a first deposition gas for coating the at least one semiconductor wafer is conducted through the epitaxy reactor, wherein an etching process in which a first etching gas and a carrier gas are conducted through the epitaxy reactor is carried out before the coating process, and wherein a cleaning process in which a second etching gas and subsequently in particular a second deposition gas are conducted through the epitaxy reactor after a predefinable number of coating processes, wherein for two or more etching processes preceding the respective coating process at least one variable which influences the etching process is set individually. Semiconductor wafers processed thereby have distinctly uniform topology.

Abstract: A semiconductor wafer comprises a substrate wafer of monocrystalline silicon and a dopant-containing epitaxial layer of monocrystalline silicon atop the substrate wafer, wherein a non-uniformity of the thickness of the epitaxial layer is not more than 0.5% and a non-uniformity of the specific electrical resistance of the epitaxial layer is not more than 2%.

Abstract: A single crystal is pulled by the FZ method, in which in a first phase, a lower end of the polycrystal is melted by the melting apparatus, in a second phase, a monocrystalline seed is attached to the lower end of the polycrystal, and in a third phase, between a lower section of the seed and the polycrystal, a thin neck section is formed whose diameter is smaller than that of the seed, where the power of the melting apparatus before the third phase is dynamically adapted in dependence on a position of a lower phase boundary (PU) between liquid material and solid material on the part of the seed, and where the power of the melting apparatus during the third phase is dynamically adapted in dependence on the position of an upper phase boundary (PO) between liquid material and solid material on the part of the polycrystal plant.

Abstract: A susceptor for holding a semiconductor wafer during the deposition of an epitaxial layer on a front side of the semiconductor wafer, has a susceptor ring and a susceptor base, and recesses below the susceptor ring in the susceptor base which are arranged in a manner distributed rotationally symmetrically. The radial width of the recesses is greater than the radial width of the susceptor such that the susceptor ring does not completely cover the recesses.