Abstract: A method of manufacturing an integrated circuit package includes: forming a substrate including: forming a core layer, and forming vias in the core layer; forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.

Abstract: A semiconductor heat spreader from a unitary metallic plate is provided. The unitary metallic plate is formed into a panel, channel walls, at least two feet, and at least one external reversing bend. The channel walls depend from the panel to define a channel between the channel walls and the panel for receiving a semiconductor therein. The feet extend from respective channel walls for attachment to a substrate.

Abstract: A method for fabricating large die package structures is provided wherein at least portions of the leadtips of at least a plurality of leadfingers of a leadframe are electrically insulated. A die is positioned on the electrically insulated leadtips. The die is electrically connected to at least a plurality of the leadfingers.

Abstract: A method of manufacturing an integrated circuit package includes: forming a substrate that includes: forming a core layer, forming vias in the core layer, and forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.

Abstract: A system is provided for an integrated circuit package including a leadframe with a lead finger. A groove is in a lead finger for a conductive bonding agent and a passive device is in the groove to be held by the conductive bonding agent.

Abstract: A method for forming a heat spreader, and the heat spreader formed thereby, are disclosed. An array heat spreader having a plurality of connected heat spreader panels is formed. Slots are formed in opposing sides of the heat spreader panels. Legs are formed on and extending downwardly from each of the heat spreader panels in at least an opposing pair of the slots on the heat spreader panels. The legs are integral with the respective heat spreader panels from which they depend.

Abstract: An integrated circuit die is provided having a body portion having a singulation side and a pedestal portion extending from the body portion and having a singulation side coplanar with the singulation side of the body portion.

Abstract: A method for fabricating large die package structures is provided wherein at least portions of the leadtips of at least a plurality of leadfingers of a leadframe are electrically insulated. A die is positioned on the electrically insulated leadtips. The die is electrically connected to at least a plurality of the leadfingers.

Abstract: An integrated circuit package comprises a substrate including a core layer with a through opening and vias. A first conductive layer is on the core layer covering the through opening and a second conductive layer is on the core layer opposite the first conductive layer in the through opening and in the vias contacting the first conductive layer. An integrated circuit die is bonded to the second conductive layer and in the through opening. Connections are between the integrated circuit die and the second conductive layer, and the integrated circuit die and the connections are encapsulated.

Abstract: A semiconductor package is provided. A semiconductor package has a die pad and a plurality of bonding fingers. A spacer is attached to the die pad, and a large die is attached to the spacer. The large die is wire bonded to the plurality of bonding fingers using a plurality of bonding wires. The die pad, plurality of bonding fingers, spacer, large die, and bonding wires are encapsulated to form the semiconductor package. The semiconductor package can be either a single or dual row package, such as a QFN or BGA package.

Abstract: A method for fabricating a semiconductor heat spreader from a unitary metallic plate is provided. The unitary metallic plate is formed into a panel, channel walls, at least two feet, and at least one external reversing bend. The channel walls depend from the panel to define a channel between the channel walls and the panel for receiving a semiconductor therein. The feet extend from respective channel walls for attachment to a substrate.

Abstract: An integrated circuit package is provided with a substrate having first and second contact pads exposed through a passivation layer on the substrate. A first metallurgy layer is over the substrate. A second metallurgy layer is over the first metallurgy layer. A protective layer is over the first contact pad.

Abstract: A semiconductor including a leadframe having a die attach paddle and a number of leads is provided. The die attach paddle has a recess to provide a number of mold dams around the periphery of the die attach paddle. An integrated circuit is positioned in the recess. Electrical connections between the integrated circuit and the number of leads are made, and an encapsulant is formed over the integrated circuit and around the number of mold dams.

Abstract: A method and apparatus for stacked die packaging provide a leadframe configured for supporting a lower semiconductor die. At least one pillar is formed on the leadframe for supporting an upper semiconductor die. The pillar is formed integrally with and of the same material as the leadframe, and is sized to have a predetermined height that is higher than the height of such a lower semiconductor die plus the height of bonding wires for such a lower semiconductor die plus a predetermined spacing between such bonding wires and the bottom of an upper semiconductor die to be supported on the at least one pillar.

Abstract: A semiconductor package is provided. A leadframe including a die attach paddle, a number of inner leads, and a number of outer leads, and a number of extended lead tips on the number of outer leads. The inner edges of the number of extended lead tips are in substantial alignment with the inner edges of the number of inner leads. A die is attached to the die attach paddle. A number of bonding wires is used to connect the die to the number of inner leads and the extended lead tips on the number of outer leads, and an encapsulant is formed over the leadframe and the die.

Abstract: An electronic device having a substrate carrier is provided. A semiconductor connected to the substrate carrier. A heat spreader having upper and lower surfaces and legs recessed below the lower surface is connected to the substrate carrier. The Z-dimension between the heat spreader and the substrate carrier is maintained over substantially the entire area of the substrate carrier.

Abstract: A stacked semiconductor package includes a substrate and a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the substrate. A second semiconductor device is mounted on the interposer.

Abstract: A system is provided for reflow soldering a part that includes: replacing air around an unsoldered part with a first inert gas; removing the first inert gas to form a vacuum around the unsoldered part; vacuum reflow soldering the unsoldered part to form a reflow-soldered part; providing a second inert gas to fill the vacuum around the reflow-soldered part; and replacing the second inert gas with air around the reflow-soldered part.

Abstract: An integrated circuit die is provided having a body portion having a singulation side and a pedestal portion extending from the body portion and having a singulation side coplanar with the singulation side of the body portion.

Abstract: A semiconductor including a leadframe having a die attach paddle and a number of leads is provided. The die attach paddle has a recess to provide a number of mold dams around the periphery of the die attach paddle. An integrated circuit is positioned in the recess. Electrical connections between the integrated circuit and the number of leads are made, and an encapsulant is formed over the integrated circuit and around the number of mold dams.