Patents Assigned to St Assembly Test Services Ltd.
  • Publication number: 20040145039
    Abstract: A method for fabricating a stacked semiconductor package includes providing a substrate and mounting a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the substrate. A second semiconductor device is then mounted on the interposer.
    Type: Application
    Filed: September 30, 2003
    Publication date: July 29, 2004
    Applicant: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Il Kwon Shim, Kambhampati Ramakrishna, Seng Guan Chow, Byung Joon Han
  • Patent number: 6759752
    Abstract: A package is provided for the mounting of IC devices. The IC die is bonded to metal traces contained in a flexible tape, the IC die with the flexible tape is attached to a stiffener (heat spreader), the various heat conducting interfaces are cured and solder balls are attached to another surface of the flexible tape.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: July 6, 2004
    Assignee: St Assembly Test Services Ltd.
    Inventors: Raymundo M. Camenforte, John Briar
  • Patent number: 6750534
    Abstract: A new method is provided to identify semiconductor devices whereby the invention provides for a shallow depression on the backside of the heat sink of the ball grid array package. This shallow depression or hole can be used for visual and optical inspection of the device orientation.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: June 15, 2004
    Assignee: ST Assembly Test Services Ltd
    Inventors: Weddie Pacio Aquien, Loreto Y. Cantillep, Setho Sing Fee
  • Patent number: 6744125
    Abstract: A new method and package is provided for the packaging of semiconductor devices. The method and package starts with a semiconductor substrate, the substrate is pre-baked. In the first embodiment of the invention, a copper foil is attached to the substrate, in the second embodiment of the invention a adhesive film is attached to the substrate. Processing then continues by attaching the die to the copper foil under the first embodiment of the invention and to the film under the second embodiment of the invention. After this the processing continues identically for the two embodiments of the invention with steps of curing, plasma cleaning, wire bonding, optical inspection, plasma cleaning and providing a molding around the die and the wires connected to the die. For the second embodiment of the invention, the film is now detached and replaced with a copper foil.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: June 1, 2004
    Assignee: St. Assembly Test Services Ltd.
    Inventors: Raymundo M. Camenforte, Dioscoro A. Merilo, Seng Guan Chow
  • Patent number: 6737298
    Abstract: A new method and assembly are provided for anchoring the heat spreader of a PBGA package to the substrate thereof. Anchor features are made part of the PBGA package. These anchor features are provided over the surface of the substrate of the PBGA package. The anchor features align with openings created in the heat spreader stand-off, thus allowing for quick and reliable positioning and anchoring of the heat spreader over the surface of the substrate of the package.
    Type: Grant
    Filed: January 23, 2002
    Date of Patent: May 18, 2004
    Assignee: St Assembly Test Services Ltd
    Inventors: Il Kwon Shim, Hermes T. Apale, Weddle Aquien, Dario Filoteo, Virgil Ararao, Leo Merilo
  • Publication number: 20040075987
    Abstract: A method for fabricating a semiconductor device heat spreader from a unitary piece of metallic material. The metallic material is stamped to form a unitary heat spreader having an upper heat dissipation region, a lower substrate contact region, and supports connecting the upper heat dissipation region and the lower substrate contact region. A recess is formed within the supports and the upper and lower regions for receiving a semiconductor device.
    Type: Application
    Filed: May 7, 2003
    Publication date: April 22, 2004
    Applicant: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Il Kwon Shim, Seng Guan Chow, Virgil Cotoco Ararao, Sheila Marie L. Alvarez, Roger Emigh
  • Publication number: 20040061205
    Abstract: A leadframe for a semiconductor die includes signal leads, ground leads, and a die support holder for supporting the semiconductor die. The die support holder has opposite surfaces and side edges therebetween. The opposite die support holder surfaces are smaller in transverse extent than the semiconductor die for supporting the die on one of the opposite die support holder surfaces such that the die extends beyond the side edges of the die support holder.
    Type: Application
    Filed: May 23, 2003
    Publication date: April 1, 2004
    Applicant: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Byung Joon Han, Byung Hoon Ahn
  • Publication number: 20040061204
    Abstract: A leadframe for a semiconductor package includes signal and ground leads, a ground plane, and a frame paddle. Supports connect the signal and ground leads, ground plane, and frame paddle in at least two different layers. At least one force release and stress relief structure is incorporated into the leadframe to free the ground plane substantially from distortion and warpage resulting from residual mechanical stresses therein.
    Type: Application
    Filed: May 23, 2003
    Publication date: April 1, 2004
    Applicant: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Byung Joon Han, Byung Hoon Ahn, Zheng Zheng
  • Patent number: 6686258
    Abstract: When leaded semiconductor packages are formed, semiconductor dies are mounted onto lead frames of a panel, via adhesive tape to be later removed. Such frames are arranged in plural snips. Each frame has plural leads, which are formed when the panel is punched and which are singulated when such strips are sawn across.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: February 3, 2004
    Assignee: ST Assembly Test Services Ltd.
    Inventor: Jae Hak Yee
  • Patent number: 6630373
    Abstract: A new design is provided for the design of a leadframe of a semiconductor package. A ground plane is added to the design of the leadframe, the ground frame is located between the leadframe and the die attach paddle over which the semiconductor device is mounted.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: October 7, 2003
    Assignee: St Assembly Test Service Ltd.
    Inventors: Jeffrey D. Punzalan, Hien Boon Tan, Zheng Zheng, Jae Hak Yee, Byung Joon Han
  • Patent number: 6627990
    Abstract: A stacked die design, and a method of forming the same, comprising: a substrate having a lower surface and an upper surface; a lower die connected to the substrate; a thermally conductive metal interposer thermally connected to the lower die and/or the substrate; and an upper die thermally connected to the metal interposer. The lower die and the upper die being spaced apart and comprising a stacked die whereby any heat generated by the upper die is transferred to the substrate by the metal interposer.
    Type: Grant
    Filed: February 6, 2003
    Date of Patent: September 30, 2003
    Assignee: St. Assembly Test Service Ltd.
    Inventors: Il Kwon Shim, Kambhampati Ramakrishna, Seng Gaun Chow
  • Patent number: 6617525
    Abstract: A molded flexible circuit assembly and method of forming a molded flexible circuit assembly which use a molded stiffener, and do not require any additional type of stiffener, are described. A molded stiffener is formed on a flexible tape at the same time molded encapsulation units are formed to encapsulate circuit die which are attached to the flexible tape. The molded stiffeners provide adequate rigidity for processing of the molded flexible circuit assembly. When the stiffeners are no longer needed they are removed at the same time the mold runners are removed. No additional processing steps are required for either the formation or removal of the molded stiffeners.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: September 9, 2003
    Assignee: St. Assembly Test Services Ltd.
    Inventors: John Briar, Raymundo M. Camenforte
  • Patent number: 6604395
    Abstract: A method and apparatus for bending probe pins that is semi-automated and uses machine vision to eliminate human error.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: August 12, 2003
    Assignee: St Assembly Test Services Ltd.
    Inventor: Chong Meng Lee
  • Publication number: 20030143777
    Abstract: A new method and package is provided for the packaging of semiconductor devices. The method and package starts with a semiconductor substrate, the substrate is pre-baked. In the first embodiment of the invention, a copper foil is attached to the substrate, in the second embodiment of the invention a adhesive film is attached to the substrate. Processing then continues by attaching the die to the copper foil under the first embodiment of the invention and to the film under the second embodiment of the invention. After this the processing continues identically for the two embodiments of the invention with steps of curing, plasma cleaning, wire bonding, optical inspection, plasma cleaning and providing a molding around the die and the wires connected to the die. For the second embodiment of the invention, the film is now detached and replaced with a copper foil.
    Type: Application
    Filed: January 9, 2003
    Publication date: July 31, 2003
    Applicant: ST Assembly Test Services Ltd.
    Inventors: Raymundo M. Camenforte, Dioscoro A. Merilo, Seng Guan Chow
  • Patent number: 6599779
    Abstract: In accordance with the objectives of the invention a new method is provided to position and secure a heat sink over the surface of a semiconductor device mounting support, the latter typically being referred to as a semiconductor substrate. A plurality of recesses is created in the surface of the substrate over which the heat sink is to be mounted. The heat sink is (conventionally and not part of the invention) provided with dimples that form the interface between the heat sink and the underlying substrate. The dimples of the heat sink are aligned with and inserted into the recesses that have been created by the invention in the underlying substrate for this purpose, firmly securing the heat sink in position with respect to the substrate.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: July 29, 2003
    Assignee: St Assembly Test Service Ltd.
    Inventors: Il Kwon Shim, Seng Guan Chow, Gerry Balanon
  • Patent number: 6597188
    Abstract: A new ground land is provided on the BGA package that allows for increasing the test sensitivity of a wire bond tester. The ground land is interconnected with a ground ring that is provided in the immediate vicinity of the BGA device. The ground land of the invention is provided such that the location of the ground land does not unduly interfere with essential functions and locations of other components that are required for the mounting of the BGA device, most preferably in a corner of the BGA device package.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: July 22, 2003
    Assignee: St Assembly Test Service Ltd.
    Inventors: Dexter Reynoso, Beng Kee Lim, Tuck Chee Albert Loh
  • Patent number: 6586925
    Abstract: A new method and apparatus is provided to quickly and reliably position, connect and dock a handler plate with a test head plate of a Universal Docking System. A handler plate is provided with roller assemblies while a test head plate is provided with matching receiver block assemblies. The roller assemblies are aligned with and partially inserted into the receiver block assemblies. Part of the roller assembly is mechanically engaged by the receiver block assembly, a mechanical linkage between an operator handle and the receiver block assembly allows the operator to complete the locking of the test head plate with the handler plate thereby at the same time establishing electrical contacts between arrays of pins that are mounted on surfaces of the handler base plate and the test head.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: July 1, 2003
    Assignee: St Assembly Test Services Ltd.
    Inventors: Ramamoorthi Ramesh, Liop-Jin Yap
  • Patent number: 6581278
    Abstract: A substrate carrier which is used through beginning assembly operations such as solder reflow for attaching ball grid array devices to flexible substrates. The carrier includes a main structural support for centerly placing the substrate. The support member include two pairs of pins protruding from the support member to engage with a matching pair of datum apertures disposed inboard of the side edges of the substrate. A plurality of high temperature magnetic inserts are affixed into holes of the support member disposed parallel and outboard of the pins. The cover has two rows of apertures for engagement with the pins of the support member is attracted by the magnetic inserts forcing the outer periphery of the cover against the top surface of the substrate.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: June 24, 2003
    Assignee: St Assembly Test Service Ltd.
    Inventor: Yuen Yew Kay
  • Publication number: 20030085462
    Abstract: A new method is provided for the establishment of a low resistivity connection between a wire bonded IC chip that is mounted on a heatsink and the heatsink of the package. A copper trace connection is allocated for this purpose on the surface of the substrate layer to which the IC chip is connected. An opening is provided in the substrate layer of the package, this opening aligns with the copper trace that has been allocated for establishing a ground connection and penetrates the substrate layer down to the surface of the underlying heatsink. The opening is filled with a conductive epoxy or an equivalent low-resistivity material thereby establishing a direct electrical connection or short between the allocated copper trace and the underlying heatsink. By connecting the ground point of the IC chip to the allocated copper trace, a direct electrical low resistivity connection is made between the ground point of the IC chip and the heatsink into which the IC chip is mounted.
    Type: Application
    Filed: December 19, 2002
    Publication date: May 8, 2003
    Applicant: ST Assembly Test Services, Ltd.
    Inventors: Weddie Aquien, John Briar, Setho Sing Fee
  • Patent number: 6544812
    Abstract: A package is provided for the mounting of IC devices. The IC die is bonded to metal traces contained in a flexible tape, the IC die with the flexible tape is attached to a stiffener (heat spreader), the various heat conducting interfaces are cured and solder balls are attached to another surface of the flexible tape.
    Type: Grant
    Filed: November 6, 2000
    Date of Patent: April 8, 2003
    Assignee: St Assembly Test Service Ltd.
    Inventors: Raymundo M. Camenforte, John Briar