Abstract: A substrate is provided. A first die is attached to the substrate. The first die is electrically connected to the substrate. A heat sink having an undercut around its periphery is attached to the first die. A second die is attached to the heat sink. The second die is electrically connected to the substrate, and the first die, the heat sink, and the second die are encapsulated.
Abstract: An integrated circuit package is provided with a connective structure having a wire bonding zone and a keep-out zone. An integrated circuit die has an undercut defining an undercut zone, which is overlapped by the keep-out zone. A wire is bonded between the integrated circuit die and the connective structure within the wire bonding zone and outside of the keep-out zone.
Type:
Application
Filed:
March 3, 2004
Publication date:
September 8, 2005
Applicant:
ST Assembly Test Service Ltd.
Inventors:
Il Kwon Shim, Virgil Ararao, Hyeong Hur, Byung Han
Abstract: A system is provided for an integrated circuit package including a leadframe having a lead finger. A groove is formed in a lead finger for a conductive bonding agent and a passive device is placed in the groove to be held by the conductive bonding agent.
Type:
Application
Filed:
February 5, 2004
Publication date:
August 11, 2005
Applicant:
ST ASSEMBLY TEST SERVICES LTD.
Inventors:
Seng Chow, Il Shim, Ming Ying, Byung Ahn
Abstract: A semiconductor package and a method of assembly therefor are provided. A semiconductor package has a die pad and a plurality of bonding fingers. A spacer is attached to the die pad, and a large die is attached to the spacer. The large die is wire bonded to the plurality of bonding fingers using a plurality of bonding wires. The die pad, plurality of bonding fingers, spacer, large die, and bonding wires are encapsulated to form the semiconductor package. The semiconductor package can be either a single or dual row package, such as a QFN or BGA package.
Abstract: A method for fabricating a semiconductor package with a substrate in a strip format is provided. Semiconductor devices are attached in a strip format to the substrate, and a thermal interface material is applied to the semiconductor devices. A flat panel heat spreader is attached to each semiconductor device. The semiconductor devices are encapsulated with open encapsulation, leaving the surface of the flat panel heat spreader opposite the substrate externally exposed. Individual semiconductor packages are then singulated from the strip format.
Type:
Application
Filed:
January 27, 2004
Publication date:
July 28, 2005
Applicant:
ST ASSEMBLY TEST SERVICES LTD.
Inventors:
Tie Wang, Virgil Ararao, Il Shim, Sheila Marie Alvarez
Abstract: A stacked semiconductor package includes a substrate and a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the substrate. A second semiconductor device is mounted on the interposer.
Type:
Application
Filed:
November 10, 2004
Publication date:
April 28, 2005
Applicant:
ST ASSEMBLY TEST SERVICES LTD.
Inventors:
Il Shim, Kambhampati Ramakrishna, Seng Chow, Byung Han
Abstract: Semiconductor packages provide a leadframe for packages that are singulated with respective predetermined package body sizes. Individual mold caps are formed on the leadframe with mold cap dimensions that are larger than the respective predetermined package body sizes. The mold caps and leadframe are singulated to the respective predetermined package body sizes.
Abstract: An integrated circuit package is provided. A substrate is provided having solder openings therein and a conductive layer thereon. The conductive layer is processed to form a plurality of pads over the solder openings in the substrate. A mask is formed over the plurality of pads and openings formed in the mask over at least two pads of the plurality of pads. An integrated circuit die is bonded over the substrate using a conductive adhesive where the conductive adhesive is placed in the openings in conductive contact with at least two pads of the plurality of pads.
Abstract: A method for forming a heat spreader, and the heat spreader formed thereby, are disclosed. An array heat spreader having a plurality of connected heat spreader panels is formed. Slots are formed in opposing sides of the heat spreader panels. Legs are formed on and extending downwardly from each of the heat spreader panels in at least an opposing pair of the slots on the heat spreader panels. The legs are integral with the respective heat spreader panels from which they depend.
Type:
Application
Filed:
August 18, 2004
Publication date:
March 3, 2005
Applicant:
ST Assembly Test Services Ltd.
Inventors:
Il Shim, Kambhampati Ramakrishna, Diane Sahakian, Seng Chow, Dario Filoteo, Virgil Ararao
Abstract: A method for fabricating a stacked semiconductor package includes providing a substrate and mounting a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the substrate. A second semiconductor device is then mounted on the interposer.
Type:
Grant
Filed:
September 30, 2003
Date of Patent:
March 1, 2005
Assignee:
ST Assembly Test Services, Ltd.
Inventors:
Il Kwon Shim, Kambhampati Ramakrishna, Seng Guan Chow, Byung Joon Han
Abstract: A method for fabricating semiconductor packages provides a leadframe for packages that are to be singulated with respective predetermined package body sizes. Individual mold caps are formed on the leadframe with mold cap dimensions that are larger than the respective predetermined package body sizes. The mold caps and leadframe are sawed to singulate packages therefrom. The sawing reduces the dimensions of the mold caps to the respective predetermined package body sizes.
Abstract: An integrated circuit package, and manufacturing method therefor, is provided. A substrate is provided having solder openings therein and a conductive layer thereon. The conductive layer is processed to form a plurality of pads over the solder openings in the substrate. A mask is formed over the plurality of pads and openings formed in the mask over at least two pads of the plurality of pads. An integrated circuit die is bonded over the substrate using a conductive adhesive where the conductive adhesive is placed in the openings in conductive contact with at least two pads of the plurality of pads.
Type:
Grant
Filed:
September 19, 2002
Date of Patent:
February 15, 2005
Assignee:
St Assembly Test Services Ltd.
Inventors:
Jian Jun Li, Il Kwon Shim, Guruprasad Badakere
Abstract: An embodiment of the present invention allows mold compound to flow underneath a substrate where the mold compound will remain in place until the process of mold formation is completed. The mold compound of the package will penetrate all available cavities where the mold compound will remain in place and harden. After hardening, the mold compound surrounding a mold anchor will support an anchored area.
Abstract: A semiconductor package and a method of assembly therefor are provided. A semiconductor package has a die pad and a plurality of bonding fingers. A spacer is attached to the die pad, and a large die is attached to the spacer. The large die is wire bonded to the plurality of bonding fingers using a plurality of bonding wires. The die pad, plurality of bonding fingers, spacer, large die, and bonding wires are encapsulated to form the semiconductor package. The semiconductor package can be either a single or dual row package, such as a QFN or BGA package.
Abstract: A semiconductor including a leadframe having a die attach paddle and a number of leads is provided. The die attach paddle has a recess to provide a number of mold dams around the periphery of the die attach paddle. An integrated circuit is positioned in the recess. Electrical connections between the integrated circuit and the number of leads are made, and an encapsulant is formed over the integrated circuit and around the number of mold dams.
Type:
Application
Filed:
May 19, 2004
Publication date:
December 16, 2004
Applicant:
ST ASSEMBLY TEST SERVICES LTD.
Inventors:
Jeffrey D. Punzalan, Jae Hun Ku, Byung Joon Han
Abstract: A semiconductor package with stacked dies and method of assembly is provided. A first die is attached to a substrate. A protective layer is placed on the first die over a central area thereof. The first die is electrically connected to the substrate. An intermediate adhesive layer is applied over the protective layer. A second die is attached to the intermediate adhesive layer and electrically connected to the substrate.
Type:
Application
Filed:
June 16, 2003
Publication date:
December 16, 2004
Applicant:
ST ASSEMBLY TEST SERVICES LTD.
Inventors:
Hyeong Ryeol Hur, Henry D. Bathan, Zigmund R. Camacho
Abstract: A system is provided for reflow soldering a part that includes: replacing air around an unsoldered part with a first inert gas; removing the first inert gas to form a vacuum around the unsoldered part; vacuum reflow soldering the unsoldered part to form a reflow-soldered part; providing a second inert gas to fill the vacuum around the reflow-soldered part; and replacing the second inert gas with air around the reflow-soldered part.
Type:
Application
Filed:
April 16, 2004
Publication date:
October 28, 2004
Applicant:
ST ASSEMBLY TEST SERVICES LTD.
Inventors:
Yonggang Jin, Shelley Yong, Puay Gek Chua, Won Sun Shin
Abstract: A new method and assembly is provided for anchoring the heat spreader of a PBGA package to the substrate thereof. Anchor features are made part of the PBGA package, these anchor features are provided over the surface of the substrate of the PBGA package. The anchor features align with openings created in the heat spreader stand-off, thus allowing for quick and reliable positioning and anchoring of the heat spreader over the surface of the substrate of the package.
Type:
Application
Filed:
March 18, 2004
Publication date:
September 16, 2004
Applicant:
ST Assembly Test Services Ltd.
Inventors:
Il Kwon Shim, Hermes T. Apale, Weddie Aquien, Dario Filoteo, Virgil Ararao, Leo Merilo
Abstract: A method for fabricating a semiconductor device heat spreader from a unitary piece of metallic material. The metallic material is stamped to form a unitary heat spreader having an upper heat dissipation region, a lower substrate contact region, and supports connecting the upper heat dissipation region and the lower substrate contact region. A recess is formed within the supports and the upper and lower regions for receiving a semiconductor device.
Type:
Grant
Filed:
May 7, 2003
Date of Patent:
August 10, 2004
Assignee:
ST Assembly Test Services Ltd.
Inventors:
Il Kwon Shim, Seng Guan Chow, Virgil Cotoco Ararao, Sheila Marie L. Alvarez, Roger Emigh
Abstract: A substrate and method of encapsulating a substrate based electronic package using injection molding and a two piece mold is described. The substrate has a barrier material formed on a gating region of the substrate. The barrier material can be formed directly over circuit wiring traces formed on the substrate thereby avoiding restrictions on the location of circuit wiring traces. The barrier material and encapsulant are chosen such that the adhesive force between the barrier material and the encapsulant is greater than the adhesive force between the barrier material and the substrate. When the mold runner is broken away the barrier material is also peeled away without damage to the substrate or circuit wiring traces.