Patents Assigned to Sumco Corporation
  • Patent number: 11969856
    Abstract: A manufacturing method of a wafer with a notch includes: polishing principal surfaces of the wafer; mirror-polishing a notch chamfered portion of the notch; mirror-polishing an outer-periphery chamfered portion of an outer peripheral portion of the wafer; and finish-polishing one of principal surfaces of the wafer, the finish-polishing being performed after performing the mirror-polishing of the notch chamfered portion, the polishing of the principal surfaces, and the mirror-polishing of the outer-periphery chamfered portion in this order.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: April 30, 2024
    Assignee: SUMCO CORPORATION
    Inventor: Kantarou Torii
  • Publication number: 20240123566
    Abstract: A processing condition setting apparatus includes a controller that selects a parameter set to be applied to the wafer processing apparatus from a plurality of parameter sets. The controller estimates, for each of the parameter sets, the post-processing characteristics of the wafer to be processed, based on the pre-processing characteristics of the wafer to be processed and the processing data, assuming that the wafer to be processed has been processed by applying each of the parameter sets. The controller calculates two or more indicators for each of the post-processing characteristics and obtains constraints on the indicators. The controller selects a parameter set, which is to be applied to the wafer processing apparatus when processing the wafer to be processed, from among the conformed parameter sets in which the indicators satisfy the constraints.
    Type: Application
    Filed: January 28, 2022
    Publication date: April 18, 2024
    Applicant: SUMCO Corporation
    Inventor: Yuji MIYAZAKI
  • Publication number: 20240128095
    Abstract: A wafer container cleaner includes a cleaning bath capable of accommodating a housing jig that houses a wafer container including a container body and a cover, liquid-supply nozzles for supplying cleaning liquid or the like into the cleaning bath, and a liquid-discharge nozzle for discharging to-be-discharged fluid out of the cleaning bath. The container body has a depth wall at a side opposite a container opening. In an accommodating state where the container body mounted on the storage fixture with the container opening facing downward is accommodated in the cleaning bath, the liquid-supply nozzles are provided so that respective liquid-supply openings through which the cleaning liquid or the like is discharged face an inner side of the depth wall and the liquid-discharge nozzle is provided so that a discharge opening through which the to-be-discharged fluid is sucked in faces a center of the inner side of the depth wall.
    Type: Application
    Filed: November 9, 2021
    Publication date: April 18, 2024
    Applicant: SUMCO CORPORATION
    Inventors: Fumitoshi IWASAKI, Katsuro WAKASUGI
  • Patent number: 11955390
    Abstract: A semiconductor wafer evaluation method includes acquiring a reflection image as a bright-field image by receiving reflected light which is obtained when irradiating one surface side of a semiconductor wafer to be evaluated with light; acquiring a scattered image as a dark-field image by receiving scattered light which is obtained when irradiating the surface side of the semiconductor wafer with light; and obtaining a distance between a bright zone that is observed in the reflection image and a bright zone that is observed in the scattered image. The semiconductor wafer to be evaluated is a semiconductor wafer in which a chamfered surface is formed in a wafer outer peripheral edge section, and the method includes evaluating a shape of a boundary part between a main surface on the surface side irradiated with the light of the semiconductor wafer to be evaluated and a chamfered surface adjacent to the main surface.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: April 9, 2024
    Assignee: SUMCO CORPORATION
    Inventors: Takahiro Nagasawa, Yasuyuki Hashimoto, Hirotaka Kato
  • Patent number: 11948819
    Abstract: Provided is a method of evaluating a silicon wafer, the method including a first determination that determines the presence or absence of an abnormality by inspecting a surface of an evaluation-target silicon wafer with a light scattering type surface inspection device; and a second determination that determines the presence or absence of an abnormality through observing, with an atomic force microscope, a region of the surface of the evaluation-target silicon wafer, where the presence of an abnormality has not been confirmed in the first determination.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: April 2, 2024
    Assignee: SUMCO CORPORATION
    Inventor: Keiichiro Mori
  • Patent number: 11948789
    Abstract: A manufacturing method of a wafer includes a first and a second resin-application grinding step, and a third surface-grinding step. The first step includes: a first formation step of forming a first coating layer; a first surface-grinding step of placing the wafer so that the first coating layer contacts a reference surface of a table and surface-grinding a first surface of the wafer; and a first removal step of removing the first coating layer. The second step includes: a second formation step of forming a second coating layer; a second surface-grinding step of placing the wafer so that the second coating layer contacts the reference surface and surface-grinding the second surface; and a second removal step of removing the second coating layer. In the third step, the wafer is placed so that the last surface-ground surface contacts the reference surface and a surface opposite the contacted surface is surface-ground.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: April 2, 2024
    Assignee: SUMCO CORPORATION
    Inventors: Toshiyuki Tanaka, Yasuyuki Hashimoto
  • Patent number: 11939695
    Abstract: A quartz glass crucible 1 having a cylindrical side wall portion 10a, a bottom portion 10b, and a corner portion 10c includes a transparent layer 11 as an innermost layer made of quartz glass, a semi-molten layer 13 as an outermost layer made of raw material silica powder solidified in a semi-molten state, and a bubble layer 12 made of quartz glass interposed therebetween. An infrared transmissivity of the corner portion 10c in a state where the semi-molten layer 13 is removed is 25 to 51%, the infrared transmissivity of the corner portion 10c in the state where the semi-molten layer 13 is removed is lower than an infrared transmissivity of the side wall portion 10a, and the infrared transmissivity of the side wall portion 10a in the state where the semi-molten layer 13 is removed is lower than an infrared transmissivity of the bottom portion 10b.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: March 26, 2024
    Assignee: SUMCO CORPORATION
    Inventors: Ken Kitahara, Masanori Fukui, Hiroshi Kishi, Tomokazu Katano, Eriko Kitahara
  • Patent number: 11935745
    Abstract: An epitaxial wafer that includes a silicon wafer and an epitaxial layer on the silicon wafer. The silicon wafer contains hydrogen that has a concentration profile including a first peak and a second peak. A hydrogen peak concentration of the first peak and a hydrogen peak concentration of the second peak are each not less than 1×1017 atoms/cm3.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: March 19, 2024
    Assignee: SUMCO CORPORATION
    Inventor: Ryosuke Okuyama
  • Patent number: 11920257
    Abstract: A method of evaluating cleanliness of a member having a silicon carbide surface, the method including bringing the silicon carbide surface into contact with a mixed acid of hydrofluoric acid, hydrochloric acid and nitric acid; concentrating the mixed acid brought into contact with the silicon carbide surface by heating; subjecting a sample solution obtained by diluting a concentrated liquid obtained by the concentration to quantitative analysis of metal components by Inductively Coupled Plasma-Mass Spectrometry; and evaluating cleanliness of the member having a silicon carbide surface on the basis of a quantitative result of metal components obtained by the quantitative analysis.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: March 5, 2024
    Assignee: SUMCO CORPORATION
    Inventors: Takashi Muramatsu, Hirokazu Kato
  • Publication number: 20240068126
    Abstract: A method of manufacturing monocrystalline silicon is provided, the method including pulling monocrystalline silicon out of a silicon melt by a Czochralski process, the silicon melt being stored in a crucible housed in a chamber, the silicon melt being added with a volatile dopant, in which a decompression rate ES for exhaust of a gas out of the chamber before the pulling of the monocrystalline silicon is within a range below at least until a pressure inside the chamber decreases from an atmospheric pressure to 80 kPa, 0 kPa/min<ES?4.2 kPa/min.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 29, 2024
    Applicant: SUMCO CORPORATION
    Inventors: Fukuo OGAWA, Hiroyuki OTA, Takashi OHARA
  • Publication number: 20240071756
    Abstract: A method for manufacturing a group III nitride semiconductor substrate, that includes: growing a first AlN buffer layer on an Si substrate at a first growth temperature; growing a second AlN buffer layer on the first AlN buffer layer at a second growth temperature higher than the first growth temperature; and growing a group III nitride semiconductor layer on the second AlN buffer layer, wherein an Al raw material and an N raw material are alternately repeatedly fed in the growing the first AlN buffer layer.
    Type: Application
    Filed: October 25, 2023
    Publication date: February 29, 2024
    Applicant: SUMCO CORPORATION
    Inventors: Koji MATSUMOTO, Toshiaki ONO, Hiroshi AMANO, Yoshio HONDA
  • Publication number: 20240060208
    Abstract: A heating portion heats a silicon melt in a quartz crucible. The heating portion includes: a heat generation portion integrally molded into a cylinder; and four power supply portions for supplying electric power to the heat generation portion. When the heating portion is divided by a virtual plane into two including a first heating region located on one side of the heat generation portion and a second heating region located on the other side of the heat generation portion with respect to the virtual plane, the virtual plane passing through a center axis of the heat generation portion and being perpendicular to the heat generation portion and parallel to a central magnetic field line of a horizontal magnetic field applied to the silicon melt, a heat generation amount of the first heating region and a heat generation amount of the second heating region are set to different values.
    Type: Application
    Filed: November 5, 2021
    Publication date: February 22, 2024
    Applicant: SUMCO CORPORATION
    Inventors: Ryusuke YOKOYAMA, Wataru SUGIMURA
  • Publication number: 20240055264
    Abstract: Provided is a wafer polishing method comprising: a step of determining a first correlation a second correlation; a step of calculating mechanical polishing rate/chemical polishing rate; a step of obtaining a relationship between the ratio of the mechanical polishing rate to the chemical polishing rate and one or more indications of wafer flatness and determining a specific range of the ratio of the mechanical polishing rate to the chemical polishing rate; a step of selecting a first target polishing solution that meets the specific range of the ratio of the mechanical polishing rate to the chemical polishing rate based on the first correlation and the second correlation; and a step of polishing wafers using the first target polishing solution. Also provided is a wafer production method including a step of performing a polishing process by the above wafer polishing method.
    Type: Application
    Filed: October 28, 2021
    Publication date: February 15, 2024
    Applicant: SUMCO Corporation
    Inventors: Chih Hao LIN, Kazushige TAKAISHI
  • Publication number: 20240055262
    Abstract: Provided is a method capable of efficiently polishing the front and back sides of a carrier plate unused after manufacture, which is used in a double-sided polishing process for semiconductor wafers. The method comprises: sandwiching a carrier plate unused after manufacture and to be polished between an upper surface plate and a lower surface plate in the double-sided polishing apparatus, and supplying a polishing liquid while relatively rotating the carrier plate to be polished, the upper surface plate, and the lower surface plate to polish both sides of the carrier plate to be polished, wherein a polishing pad including, on its surface, an abrasive grain-containing layer in which abrasive grains of 2 ?m or more in grain size are embedded is used as a polishing pad in a double-sided polishing apparatus.
    Type: Application
    Filed: November 19, 2021
    Publication date: February 15, 2024
    Applicant: SUMCO Corporation
    Inventors: Shunsuke MIKURIYA, Shinya TAKUBO
  • Patent number: 11898246
    Abstract: A vapor deposition device is provided that can ameliorate or improve the LPD quality. A vapor deposition device includes a first holder that supports a carrier at a topmost-level and a second holder that supports the carrier under the first holder in a load-lock chamber, and a second robot mounts a before-treatment wafer extracted from a wafer storage container on the carrier standing by at the first holder in the load-lock chamber.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: February 13, 2024
    Assignee: SUMCO CORPORATION
    Inventors: Naoyuki Wada, Yu Minamide
  • Patent number: 11890719
    Abstract: In a method of polishing a silicon wafer, a final polishing step includes an upstream polishing step and a subsequent finish polishing step. In the upstream polishing step, as a polishing agent, a first alkaline aqueous solution containing abrasive grains with a density of 1×1014/cm3 or more is first supplied, and the supply is then switched to a supply of a second alkaline aqueous solution containing a water-soluble polymer and abrasive grains with a density of 5×1013/cm3 or less. In the finish polishing step, as a polishing agent, a third alkaline aqueous solution containing a water-soluble polymer and abrasive grains with a density of 5×10?13/cm3 or less is supplied. Thus, the formation of not only PIDs but also scratches with small depth can be suppressed.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: February 6, 2024
    Assignee: SUMCO CORPORATION
    Inventor: Shuhei Matsuda
  • Patent number: 11885038
    Abstract: A convection pattern estimation method of a silicon melt includes: applying a horizontal magnetic field of 0.2 tesla or more to a silicon melt in a rotating quartz crucible with use of a pair of magnetic bodies disposed across the quartz crucible; before a seed crystal is dipped into the silicon melt to which the horizontal magnetic field is applied; measuring temperatures at a first and second measurement points positioned on a first imaginary line that passes through a center of a surface of the silicon melt and is not in parallel with a central magnetic field line of the horizontal magnetic field as viewed vertically from above; and estimating a direction of a convection flow in a plane in the silicon melt orthogonal to the direction in which the horizontal magnetic field is applied on a basis of the measured temperatures of the first and second measurement points.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: January 30, 2024
    Assignee: SUMCO CORPORATION
    Inventors: Wataru Sugimura, Ryusuke Yokoyama, Toshiyuki Fujiwara, Toshiaki Ono
  • Patent number: 11888036
    Abstract: A manufacturing method of an epitaxial silicon wafer includes forming an epitaxial film made of silicon on a surface of a silicon wafer in a trichlorosilane gas atmosphere; and setting the nitrogen concentration of the surface of the epitaxial film through inward diffusion from a nitride film on the epitaxial film, the nitride film being formed by subjecting the silicon wafer provided with the epitaxial film to heat treatment in a nitrogen atmosphere.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: January 30, 2024
    Assignee: SUMCO CORPORATION
    Inventors: Kazuya Kodani, Toshiaki Ono, Kazuhisa Torigoe
  • Publication number: 20240025008
    Abstract: A method of polishing a silicon wafer, including a final polishing step including a pre-stage polishing step and a subsequent finish polishing step. The finish polishing step in the final polishing step includes a finish slurry polishing step using a polishing solution having an abrasive grain density of 1×1013/cm3 or more as the second polishing solution; and a pre-polishing step using a polishing solution having an abrasive grain density of 1×1010/cm3 or less as the second polishing solution, the pre-polishing step being performed prior to the finish slurry polishing step. A method of producing a silicon wafer, including the steps of: forming a notch portion on a periphery of a single crystal silicon ingot grown by the Czochralski process; slicing the ingot to obtain a silicon wafer; and subjecting the resulting silicon wafer to the above method of polishing a silicon wafer.
    Type: Application
    Filed: August 25, 2021
    Publication date: January 25, 2024
    Applicant: SUMCO CORPORATION
    Inventors: Masahiro MURAKAMI, Ryoya TERAKAWA
  • Publication number: 20240026564
    Abstract: A production method of monocrystalline silicon includes: growing the monocrystalline silicon having a straight-body diameter in a range from 301 mm to 330 mm that is pulled up through a Czochralski process from a silicon melt including a dopant in a form of arsenic; controlling a resistivity of the monocrystalline silicon at the straight-body start point to fall within a range from 2.50 m?cm to 2.90 m?cm; and subsequently sequentially decreasing the resistivity of the monocrystalline silicon to fall within a range from 1.6 m?cm to 2.0 m?cm at a part of the monocrystalline silicon.
    Type: Application
    Filed: October 3, 2023
    Publication date: January 25, 2024
    Applicant: SUMCO CORPORATION
    Inventors: Yasufumi KAWAKAMI, Koichi MAEGAWA