Patents Assigned to Sumco Corporation
  • Publication number: 20230031070
    Abstract: A monocrystalline silicon includes a shoulder, a straight body, and a tail. The straight body includes: a first straight body having a first diameter d1; and a second straight body provided closer to the shoulder than the first straight body is and having a second diameter d2 larger than the first diameter d1 by from 3.5% to 15%. Firstly, a resistivity at a start point of the straight body connected to the shoulder is set to a first resistivity. Subsequently, the monocrystalline silicon is pulled up and grown to form the first straight body, and a resistivity at a start point of the first straight body is set to a second resistivity lower than the first resistivity.
    Type: Application
    Filed: December 21, 2020
    Publication date: February 2, 2023
    Applicant: SUMCO CORPORATION
    Inventors: Takashi IZEKI, Yasuhito NARUSHIMA
  • Publication number: 20230033913
    Abstract: Provided is a cleaning apparatus and a cleaning method for semiconductor wafers that can hinder a mist of a cleaning solution from being adhered to a surface of a semiconductor wafer during cleaning of the semiconductor wafer. In a cleaning apparatus 1 for a semiconductor wafer, a spin cup 20 has an annular side wall portion 21; an inclined portion 22 that is inclined toward the rotating table 13; and an annular bent portion 23. The height position h21 of the upper end portion 21c of the side wall portion 21 is set at a position lower than the height position h14a of the upper end portion 14a of the wafer retainer portion 14, and the inclination angle ?22 of the inclined portion to a horizontal plane and the width w of the inclined portion satisfy a formula (A): ?22(°)??0.65×w (mm)+72.
    Type: Application
    Filed: August 17, 2020
    Publication date: February 2, 2023
    Applicant: SUMCO CORPORATION
    Inventors: Kaito NODA, Kazuhiro OHKUBO, Yuki NAKAO, Michihiko TOMITA
  • Publication number: 20230033545
    Abstract: Provided is a method of transferring a semiconductor wafer to a single-side polishing apparatus without forming scratches on the surface of the semiconductor wafer. The method includes: starting to splay the liquid from each spray hole; placing the semiconductor wafer on the retainer portion to hold a surface of the semiconductor wafer by suction without contact, and raising the tray to attach the semiconductor wafer to the polishing head, wherein a period of time from a point at which the semiconductor wafer is held by the retainer portion to a point at which the attaching of the semiconductor wafer W to the polishing head is completed is 5 s or more, or wherein a ratio of a total area of the protrusions to an area of the semiconductor wafer is 15% or more.
    Type: Application
    Filed: October 13, 2020
    Publication date: February 2, 2023
    Applicant: SUMCO CORPORATION
    Inventor: Ryoya TERAKAWA
  • Publication number: 20230023541
    Abstract: A system and method for producing a single crystal can prevent calculation and setting mistakes and provide an adequate correction amount in the next batch. A single crystal manufacturing system includes a pulling-up apparatus that calculates a diameter measurement value of a single crystal during a pulling-up process, calculates a first diameter of the single crystal by correcting the diameter measurement value using a diameter correction coefficient, and controls crystal pulling-up conditions based on the first diameter. A diameter measuring apparatus measures a diameter of the single crystal pulled up by the pulling-up apparatus to calculate a second diameter of the single crystal. A database server acquires the first diameter and the second diameter. The database server calculates a correction amount of the diameter correction coefficient from the first and second diameters obtained at diameter measurement positions which coincide with each other under room temperature.
    Type: Application
    Filed: October 30, 2020
    Publication date: January 26, 2023
    Applicant: SUMCO Corporation
    Inventors: Kenichi Nishioka, Keiichi Takanashi
  • Publication number: 20230025927
    Abstract: A vapor deposition device is provided that can correct a positional offset of a carrier in a rotation direction relative to a wafer when the vapor deposition device is viewed in a plan view. The vapor deposition device includes a load-lock chamber provided with a holder for supporting the carrier, and the carrier and the holder are provided with a correction mechanism that corrects a position of the carrier in a rotation direction when the vapor deposition device is viewed in a plan view.
    Type: Application
    Filed: October 15, 2020
    Publication date: January 26, 2023
    Applicant: SUMCO CORPORATION
    Inventor: Yu MINAMIDE
  • Patent number: 11559869
    Abstract: A wafer edge polishing apparatus includes a cleaning mechanism exhibiting a superb effect of cleaning slurry residue adhered on a chuck table. This edge polishing device is provided with: a chuck table which sucks/holds a wafer; a rotation drive mechanism which rotates the chuck table; an edge polishing unit which polishes an edge of the wafer while supplying slurry to the wafer, which is rotating while being sucked/held by the chuck table; and a cleaning unit which removes slurry residue on the chuck table. The cleaning unit includes a cleaning head, and cleans the chuck table through high-pressure cleaning and brush-cleaning by using the cleaning head, wherein the cleaning head is provided with a high-pressure jet nozzle and a brush surrounding the periphery of the high-pressure jet nozzle.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: January 24, 2023
    Assignee: SUMCO CORPORATION
    Inventors: Makoto Ando, Tatsunori Izumi, Ryuichi Tanimoto, Yuhei Matsunaga, Yasuo Yamada
  • Publication number: 20230015459
    Abstract: A wafer manufacturing system includes a wafer manufacturing device provided with a sensor; a host PC that is connected to the wafer manufacturing device via a data communication line; a logic controller that samples and stores an analog output signal of the sensor; and a relay PC that extracts tracking information transmitted on the data communication line for a wafer or a single crystal that is being processed by the wafer manufacturing device and sends the tracking information to the logic controller, and the logic controller stores a digital value of the analog output signal of the sensor in association with the tracking information that is sent from the relay PC.
    Type: Application
    Filed: October 21, 2020
    Publication date: January 19, 2023
    Applicant: SUMCO Corporation
    Inventor: Shigeru DAIGO
  • Patent number: 11554458
    Abstract: A polishing head of a wafer polishing apparatus is provided with: a membrane head that can independently control a center control pressure pressing a center portion of a wafer, and an outer periphery control pressure pressing an outer peripheral portion of the wafer; an outer ring integrated with the membrane head so as to configure the outer peripheral portion of the membrane head; and a contact type retainer ring provided outside the membrane head. The membrane head has a central pressure chamber of a single compartment structure that controls the center control pressure, and an outer peripheral pressure chamber that is provided above the central pressure chamber, and that controls the outer periphery control pressure. A position of a lower end of the outer ring reaches at least a position of an inner bottom surface of the central pressure chamber.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: January 17, 2023
    Assignee: SUMCO CORPORATION
    Inventors: Yuki Nakano, Katsuhisa Sugimori, Kazuaki Kozasa, Jiro Kajiwara, Katsutoshi Yamamoto, Takayuki Kihara, Ryoya Terakawa
  • Publication number: 20230009579
    Abstract: A vapor deposition device is provided that can suppress an influence on an epitaxial layer which is caused by a position of a lift pin without adjusting an upper and lower heating ratio of a wafer. A reaction chamber is provided with a susceptor on which a carrier is placed, and a carrier lift pin which moves the carrier vertically relative to the susceptor; and the carrier lift pin is installed outside of an outer edge of the wafer when a state where the carrier supporting the wafer is mounted on the susceptor is viewed in a plan view.
    Type: Application
    Filed: November 16, 2020
    Publication date: January 12, 2023
    Applicant: SUMCO CORPORATION
    Inventors: Yu MINAMIDE, Naoyuki WADA
  • Patent number: 11551922
    Abstract: Provided are a method of polishing a silicon wafer and a method of producing a silicon wafer which can reduce the formation of step-forming microdefects on a silicon wafer. The method includes: a double-side polishing step of performing polishing on front and back surfaces of a silicon wafer; a notch portion polishing step of performing polishing on a beveled portion of a notch portion of the silicon wafer after the double-side polishing step; a peripheral beveled portion polishing step of performing polishing on the beveled portion on the periphery of the silicon wafer other than the beveled portion of the notch portion after the notch portion polishing step; and a finish polishing step of performing finish polishing on the front surface of the silicon wafer after the peripheral beveled portion polishing step. The notch portion polishing step is performed in a state where the front surface is wet with water.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: January 10, 2023
    Assignee: SUMCO CORPORATION
    Inventor: Tsuyoshi Morita
  • Publication number: 20220415666
    Abstract: Provided is a wafer polishing method capable of improving nanotopography characteristics within a site on the surface of a wafer having a 2 mm square area or a small area equivalent thereto and a silicon wafer polished by the wafer polishing method, and further provided is a method of chemical-mechanical polishing the surface of a wafer through a polishing step in two or more polishing steps with different polishing rates, in which the in-plane thickness variation (standard deviation) of a polishing pad 150 used in a polishing step with a machining allowance of 0.3 ?m or more is 2.0 ?m or less.
    Type: Application
    Filed: October 21, 2020
    Publication date: December 29, 2022
    Applicant: SUMCO CORPORATION
    Inventors: Kazuaki KOZASA, Katsuhisa SUGIMORI, Kazuki NISHIOKA, Tsuyoshi MORITA
  • Patent number: 11535546
    Abstract: A silica glass crucible includes a cylindrical side wall portion, a curved bottom portion, and a corner portion that is provided between the side wall portion and the bottom portion and has a higher curvature than a curvature of the bottom portion, in which a first region provided from a crucible inner surface to a middle in a thickness direction, a second region that is provided outside the first region in the thickness direction and has a different strain distribution from the first region, and a third region that is provided outside the second region in the thickness direction and up to the crucible outer surface and has a different strain distribution from the second region, are provided, and internal residual stresses of the first region and the third region are compressive stresses, whereas an internal residual stress of the second region includes a tensile stress.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: December 27, 2022
    Assignee: SUMCO CORPORATION
    Inventors: Ken Kitahara, Masaru Sato, Takuma Yoshioka
  • Publication number: 20220406599
    Abstract: A control device includes a calculation unit generating control information for an epitaxial growth apparatus; and a storage unit storing measurement values for an epitaxial film formed by the epitaxial growth apparatus and measurement values for epitaxial films formed by a plurality of other epitaxial growth apparatuses that are provided in the same production line as the epitaxial growth apparatus that needs new control. The calculation unit generates and outputs information for controlling at least one of the supply time of a source gas and the flow rate of a dopant gas in the epitaxial growth apparatus based on the measurement values for the epitaxial film formed by the epitaxial growth apparatus that needs new control and the measurement values of the epitaxial films formed by the other epitaxial growth apparatuses in the same production line that are in operation concurrently with the epitaxial growth apparatus.
    Type: Application
    Filed: June 17, 2022
    Publication date: December 22, 2022
    Applicant: SUMCO Corporation
    Inventor: Naoyuki WADA
  • Patent number: 11515263
    Abstract: A method of producing a silicon wafer includes: a laser mark printing step of printing a laser mark having a plurality of dots on a silicon wafer; an etching step of performing etching on at least a laser-mark printed region in a surface of the silicon wafer; and a polishing step of performing polishing on both surfaces of the silicon wafer having been subjected to the etching step. In the laser mark printing step, each of the plurality of dots is formed by a first step of irradiating a predetermined position on a periphery of the silicon wafer with laser light of a first beam diameter thereby forming a first portion of the dot and a second step of irradiating the predetermined position with laser light of a second beam diameter that is smaller than the first beam diameter thereby forming a second portion of the dot.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: November 29, 2022
    Assignee: SUMCO CORPORATION
    Inventor: Yoichiro Hirakawa
  • Publication number: 20220373478
    Abstract: The method includes detecting a COP in a surface of a reference wafer with a laser surface inspection apparatus to be calibrated and an apparatus for calibration that obtains an X coordinate position and a Y coordinate position of the COP; determining a COP that is detected as the same COP with a determination criterion that a positional difference between a detected position obtained by the laser surface inspection apparatus to be calibrated and a detected position obtained by the apparatus for calibration on the reference wafer surface is within a threshold range; and calibrating the coordinate position identification accuracy of the laser surface inspection apparatus to be calibrated by adopting the X and Y coordinate positions obtained by the apparatus for calibration as true values of the X and Y coordinate positions.
    Type: Application
    Filed: October 6, 2020
    Publication date: November 24, 2022
    Applicant: SUMCO CORPORATION
    Inventors: Keiichiro MORI, Takahiro NAGASAWA
  • Publication number: 20220364260
    Abstract: Provided is a point detect simulator which makes it possible to determine the distribution of point defects in a silicon single crystal in consideration of the thermal stress of the silicon single crystal being grown. A point defect simulator 1 is a point defect simulator calculating the concentration profiles of vacancies and interstitial silicon during pulling of a silicon single crystal using a convection-diffusion equation reflecting the consideration of thermal stress in the silicon single crystal, and includes an analysis unit used to fit calculation results to experimental results using stress coefficients that are the coefficients of stress terms as a fitting parameter.
    Type: Application
    Filed: August 12, 2020
    Publication date: November 17, 2022
    Applicant: SUMCO CORPORATION
    Inventor: Ryota SUEWAKA
  • Patent number: 11501996
    Abstract: Provided is a susceptor which makes it possible to increase the circumferential flatness uniformity of an epitaxial layer of an epitaxial silicon wafer. A susceptor 100 is provided with a concave counterbore portion on which a silicon wafer W is placed, and the radial distance L between the center of the susceptor and an opening edge of the counterbore portion varies at 90° periods in the circumferential direction. Meanwhile, when the angle at which the radial distance L is minimum is 0°, the radial distance L is a minimum value L1 at 90°, 180°, and 270°; and the radial distance L is a maximum value L2 at 45°, 135°, 225°, and 315°. Accordingly, the pocket width Lp also varies in conformance with the variations of the radial distance L. The opening edge 110C describes four elliptical arcs being convex radially outward when the susceptor 100 is viewed from above.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: November 15, 2022
    Assignee: SUMCO CORPORATION
    Inventor: Kazuhiro Narahara
  • Publication number: 20220331906
    Abstract: Provided is a laser mark printing method and a method of producing a laser-marked silicon wafer that can reduce the machining strain left around dots constituting a laser mark. In a method of printing a laser mark having a plurality of dots on a silicon wafer, the plurality of dots are formed using laser light having a wavelength in the ultraviolet region.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 20, 2022
    Applicant: SUMCO CORPORATION
    Inventor: Yoichiro HIRAKAWA
  • Patent number: 11473210
    Abstract: Provided is a heat shielding member, a single crystal pulling apparatus, and a method of producing a single crystal silicon ingot, which can expand the margin of the crystal pulling rate with which a defect-free single crystal silicon can be obtained. A heat shielding member is provided in a single crystal pulling apparatus, the heat shielding member including a cylindrical tubular portion surrounding an outer circumferential surface of the single crystal silicon ingot; and a ring-shaped projecting portion under the tubular portion. The projecting portion has an upper wall, a bottom wall, and two vertical walls, a heat insulating material with a ring shape is provided in the space surrounded by those walls; and a gap between the vertical wall adjacent to the single crystal silicon ingot and the heat insulating material.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: October 18, 2022
    Assignee: SUMCO CORPORATION
    Inventors: Kaoru Kajiwara, Ryota Suewaka, Shunji Kuragaki, Kazumi Tanabe
  • Patent number: 11473211
    Abstract: A method of estimating an oxygen concentration in monocrystalline silicon, which is pulled up by a pull-up device having a hot zone with a plane-asymmetric arrangement with respect to a plane defined by a crystal pull-up shaft and an application direction of a horizontal magnetic field, includes, in at least one of a neck-formation step or a shoulder-formation step for the monocrystalline silicon: a step of measuring a surface temperature of a silicon melt at a point defining a plane-asymmetric arrangement of a hot zone, and a step of estimating the oxygen concentration in a straight body of the pulled-up monocrystalline silicon based on the measured surface temperature of the silicon melt and a predetermined relationship between the surface temperature of the silicon melt and the oxygen concentration in the monocrystalline silicon.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: October 18, 2022
    Assignee: SUMCO CORPORATION
    Inventors: Shin Matsukuma, Kazuyoshi Takahashi, Toshinori Seki, Tegi Kim, Ryusuke Yokoyama