Abstract: A re-programmable antifuse field programmable gate array (FPGA) integrated circuit, the FPGA comprising: a plurality of CeRAM resistive switching elements forming a connection block, the switching elements capable of being switched from a conductive (ON) state to a non-conductive (OFF) state and back to a conductive (ON) state; a plurality of logic elements forming a logic block; and a programming circuit for turning the CeRAM switching elements OFF and ON to connect the logic elements to form the FPGA.

Abstract: A re-programmable antifuse field programmable gate array (FPGA) integrated circuit, the FPGA comprising: a plurality of CeRAM resistive switching elements forming a connection block, the switching elements capable of being switched from a conductive (ON) state to a non-conductive (OFF) state and back to a conductive (ON) state; a plurality of logic elements forming a logic block; and a programming circuit for turning the CeRAM switching elements OFF and ON to connect the logic elements to form the FPGA.

Abstract: A non-volatile resistive switching memory that includes a homogeneous material which changes between the insulative and conductive states due to correlations between electrons, particularly via a Mott transition. The material is crystallized into the conductive state and does not require electroforming.

Abstract: An integrated circuit memory cell including: a semiconductor having a first active area, a second active area, and a channel between the active areas; and a layer of a variable resistance material (VRM) directly above the channel. In one embodiment, there is a first conductive layer between the VRM and the channel and a second conductive layer directly above the VRM layer. The VRM preferably is a correlated electron material (CEM). The memory cell comprises a FET, such as a JFET or a MESFET. In another embodiment, there is a layer of an insulating material between the VRM and the channel. In this case, the memory cell may include a MOSFET structure.

Abstract: An integrated circuit memory cell including: a semiconductor having a first active area, a second active area, and a channel between the active areas; and a layer of a variable resistance material (VRM) directly above the channel. In one embodiment, there is a first conductive layer between the VRM and the channel and a second conductive layer directly above the VRM layer. The VRM preferably is a correlated electron material (CEM). The memory cell comprises a FET, such as a JFET or a MESFET. In another embodiment, there is a layer of an insulating material between the VRM and the channel. In this case, the memory cell may include a MOSFET structure.

Abstract: A non-volatile resistive switching memory that includes a material which changes between the insulative and conductive states. The material is stabilized against charge trapping by oxygen vacancies by an extrinsic ligand, such as carbon.

Abstract: A non-volatile resistive switching memory that includes a material which changes between the insulative and conductive states. The material is stabilized against charge trapping by oxygen vacancies by an extrinsic ligand, such as carbon.

Abstract: A three-dimensional (“3-D”) memory capacitor comprises a bottom electrode, a ferroelectric thin film, and a top electrode that conform to a 3-D surface of an insulator layer. The capacitance area is greater than the horizontal footprint area of the capacitor. Preferably, the footprint of the capacitor is less than 0.2 nm2, and the corresponding capacitance area is typically in a range of from 0.4 nm2 to 1.0 nm2 The ferroelectric thin film preferably has a thickness not exceeding 60 nm. A capacitor laminate including the bottom electrode, ferroelectric thin film, and the top electrode preferably has a thickness not exceeding 200 nm. A low-thermal-budget MOCVD method for depositing a ferroelectric thin film having a thickness in a range of from 30 nm to 90 nm includes an RTP treatment before depositing the top electrode and an RTP treatment after depositing the top electrode and etching the ferroelectric layer.

Abstract: A non-volatile resistive switching memory that includes a homogeneous material which changes between the insulative and conductive states due to correlations between electrons, particularly via a Mott transition. The material is crystallized into the conductive state and does not require electroforming.

Abstract: A method of making a variable resistance material (VRM), the method comprising providing a precursor comprising a metallorganic or organometallic solvent containing a metal moiety suitable for forming the VRM, depositing the precursor on a substrate to form a thin film of the precursor, and heating the thin film to form the VRM. The preferred solvent comprises octane.

Abstract: A non-volatile resistive switching memory that includes a material which changes between the insulative and conductive states. The material is stabilized against charge trapping by oxygen vacancies by an extrinsic ligand, such as carbon.

Abstract: An integrated circuit memory cell including: a semiconductor having a first active area, a second active area, and a channel between the active areas; and a layer of a variable resistance material (VRM) directly above the channel. In one embodiment, there is a first conductive layer between the VRM and the channel and a second conductive layer directly above the VRM layer. The VRM preferably is a correlated electron material (CEM). The memory cell comprises a FET, such as a JFET or a MESFET. In another embodiment, there is a layer of an insulating material between the VRM and the channel. In this case, the memory cell may include a MOSFET structure.

Abstract: A 1T1R resistive memory array comprised of chains of memory cells, where each memory cell is composed of a resistive element in parallel with a switch. Such chains of memory cells are non-volatile and provide for each of the memory cells to be randomly accessed.

Abstract: A ferroelectric memory including a bit line pair, a drive line parallel to and located between the bit lines, and an associated memory cell. The memory cell includes two capacitors, each capacitor connected to one of said bit lines via a transistor, and each capacitor is also connected to the drive line via a transistor. The gates of all three of the transistors are connected to a word line perpendicular to the bit lines and drive line, so that when the word line is not selected, the capacitors are completely isolated from any disturb. The bit lines may be complementary and the cell a one-bit cell, or the cell may be a two-bit cell. In the latter case, the memory includes a dummy cell identical to the above cell, in which the two dummy capacitors are complementary. A sense amplifier with three bit line inputs compares the cell bit line with a signal derived from the two dummy bit lines. The logic states of the dummy capacitors alternate in each cycle, preventing imprint and fatigue.

Abstract: A nonconductive hydrogen barrier layer is deposited on a substrate and completely covers the surface area over a memory capacitor and a MOSFET switch of an integrated circuit memory cell. A portion of an insulator layer adjacent to the bottom electrode of a memory capacitor is removed by etching to form a moat region. A nonconductive oxygen barrier layer is deposited to cover the sidewall and bottom of the moat. The nonconductive oxygen barrier layer and a conductive diffusion barrier beneath the capacitor together provide a substantially continuous diffusion barrier between the capacitor and a switch. Also, the nonconductive hydrogen barrier layer, the nonconductive oxygen barrier, and the conductive diffusion barrier substantially completely envelop the capacitor, in particular a ferroelectric thin film in the capacitor.

Abstract: A device and method of reading a ferroelectric memory, including providing a ferroelectric memory including a ferroelectric memory cell, a charge integrator, and a bit line connecting the ferroelectric memory cell and the charge integrator. Pulses are applied to the ferroelectric memory cell, where each of the pulses are of a value lower than that which will destroy data stored in the memory cell. Output voltage values from the ferroelectric memory cell are accumulated by the charge integrator in response to each pulse. The output of the charge integrator may be read to determine whether the datum value stored in the memory cell is a logic high or low value. In one embodiment, the output of the charge integrator is read at a predetermined time after starting the pulses.

Abstract: A three-dimensional (“3-D”) memory capacitor comprises a bottom electrode, a ferroelectric thin film, and a top electrode that conform to a 3-D surface of an insulator layer. The capacitance area is greater than the horizontal footprint area of the capacitor. Preferably, the footprint of the capacitor is less than 0.2 nm2, and the corresponding capacitance area is typically in a range of from 0.4 nm2 to 1.0 nm2 The ferroelectric thin film preferably has a thickness not exceeding 60 nm. A capacitor laminate including the bottom electrode, ferroelectric thin film, and the top electrode preferably has a thickness not exceeding 200 nm. A low-thermal-budget MOCVD method for depositing a ferroelectric thin film having a thickness in a range of from 30 nm to 90 nm includes an RTP treatment before depositing the top electrode and an RTP treatment after depositing the top electrode and etching the ferroelectric layer.

Abstract: A three-dimensional (“3-D”) memory capacitor comprises a bottom electrode, a ferroelectric thin film, and a top electrode that conform to a 3-D surface of an insulator layer. The capacitance area is greater than the horizontal footprint area of the capacitor. Preferably, the footprint of the capacitor is less than 0.2 nm2, and the corresponding capacitance area is typically in a range of from 0.4 nm2 to 1.0 nm2 The ferroelectric thin film preferably has a thickness not exceeding 60 nm. A capacitor laminate including the bottom electrode, ferroelectric thin film, and the top electrode preferably has a thickness not exceeding 200 nm. A low-thermal-budget MOCVD method for depositing a ferroelectric thin film having a thickness in a range of from 30 nm to 90 nm includes an RTP treatment before depositing the top electrode and an RTP treatment after depositing the top electrode and etching the ferroelectric layer.

Abstract: A hydrogen diffusion barrier in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of a metal oxide, such as a ferroelectric layered superlattice material, in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following chemical compounds: strontium tantalate, bismuth tantalate, tantalum oxide, titanium oxide, zirconium oxide and aluminum oxide. The hydrogen barrier layer is amorphous and is made by a MOCVD process at a temperature of 450° C. or less. A supplemental hydrogen barrier layer comprising a material selected from the group consisting of silicon nitride and a crystalline form of one of said hydrogen barrier layer materials is formed adjacent to said hydrogen diffusion barrier.

Abstract: A pyrometer cell comprises a first ferroelectric capacitor, a second ferroelectric capacitor, and a difference circuit for determining the difference between the polarization charge, voltage, or current between the first and second ferroelectric capacitors. The cell is pulsed a plurality of times and an integrator circuit connected to the difference circuit provides an enhanced output signal representative of the integrated difference. An infrared imager is formed by an array of the pyrometer cells, with one ferroelectric capacitor in each cell exposed to an infrared source and the other ferroelectric capacitor not exposed to the infrared source.