Patents Assigned to Symetrix Corporation
  • Publication number: 20030098497
    Abstract: A hydrogen diffusion barrier in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of a metal oxide, such as a ferroelectric layered superlattice material, in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following chemical compounds: strontium tantalate, bismuth tantalate, tantalum oxide, titanium oxide, zirconium oxide and aluminum oxide. The hydrogen barrier layer is amorphous and is made by a MOCVD process at a temperature of 450° C. or less. A supplemental hydrogen barrier layer comprising a material selected from the group consisting of silicon nitride and a crystalline form of one of said hydrogen barrier layer materials is formed adjacent to said hydrogen diffusion barrier.
    Type: Application
    Filed: November 29, 2001
    Publication date: May 29, 2003
    Applicant: Symetrix Corporation
    Inventors: Narayan Solayappan, Jolanta Celinska, Vikram Joshi, Carlos A. Paz de Araujo, Larry D. McMillan
  • Patent number: 6570202
    Abstract: A hydrogen barrier layer is formed above a ferroelectric thin film in an integrated circuit. The hydrogen barrier layer is directly over a protected segment of the ferroelectric thin film, while a sacrificial segment of the ferroelectric thin film extends laterally beyond the edges of the hydrogen barrier layer. The sacrificial segment absorbs hydrogen so that it cannot diffuse laterally into the protected segment of the ferroelectric thin film. After it absorbs hydrogen, the sacrificial segment is etched away to allow electrical connection to circuit layers below it. The ferroelectric thin film preferably comprises a layered superlattice compound. Excess bismuth or niobium added to the standard precursor solution of a strontium bismuth tantalum niobate compound helps to reduce hydrogen degradation of the ferroelectric properties.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: May 27, 2003
    Assignees: Symetrix Corporation, NEC Corporation
    Inventors: Joseph D. Cuchiaro, Akira Furuya, Carlos A. Paz de Araujo, Yoichi Miyasaka
  • Patent number: 6562678
    Abstract: A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.
    Type: Grant
    Filed: March 7, 2000
    Date of Patent: May 13, 2003
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Uchiyama, Narayan Solayappan, Carlos A. Paz de Araujo
  • Patent number: 6559469
    Abstract: An integrated circuit includes a layered superlattice material having the formula A1w1+a1A2w2+a2 . . . Ajwj+ajS1x1+s1S2x2+s2 . . . Skxk+skB1y1+b1B2y2+b2 . . . Blyl+blQz−q, where A1, A2 . . . Aj represent A-site elements in a perovskite-like structure, S1, S2 . . . Sk represent superlattice generator elements, B1, B2 . . . B1 represent B-site elements in a perovskite-like structure, Q represents an anion, the superscripts indicate the valences of the respective elements, the subscripts indicate the number of atoms of the element in the unit cell, and at least w1 and y1 are non-zero. Some of these materials are extremely low fatigue ferroelectrics and are applied in ferroelectric FETs in non-volatile memories. Others are high dielectric constant materials that do not degrade or break down over long periods of use and are applied as the gate insulator in volatile memories.
    Type: Grant
    Filed: October 11, 2000
    Date of Patent: May 6, 2003
    Assignee: Symetrix Corporation
    Inventors: Carlos A. Paz de Araujo, Larry D. McMillan, Vikram Joshi, Narayan Solayappan, Joseph D. Cuchiaro
  • Publication number: 20030080325
    Abstract: A method of forming a Bi-layered superlattice material on a substrate using chemical vapor deposition of a precursor solution of trimethylbismuth and a metal compound dissolved in an organic solvent. The precursor solution is heated and vaporized prior to deposition of the precursor solution on an integrated circuit substrate by chemical vapor deposition. No heating steps including a temperature of 650° C. or higher are used.
    Type: Application
    Filed: October 26, 2001
    Publication date: May 1, 2003
    Applicant: Symetrix Corporation and Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Uchiyama, Narayan Solayappan, Carlos A. Paz de Araujo
  • Patent number: 6541279
    Abstract: A high dielectric constant insulator including a thin film of a metal oxide selected from the group consisting of tungsten-bronze-type oxides, pyrochlore-type oxides, and combinations of Bi2O3 with an oxide selected from the group consisting of perovskites and pyrochlore-type oxides. An embodiment contains metal oxides represented by the general stoichiometric formulas AB2O6, A2B2O7 and A2Bi2B2O10, wherein A represents A-site atoms selected from the group of metals consisting of Ba, Bi, Sr, Pb, Ca, K, Na and La; and B represents B-site atoms selected from the group of metals consisting of Ti, Zr, Ta, Hf, Mo, W and Nb. Preferably, the metal oxides are (BaxSr1−x)(TayNb1−y)2O6, where 0≦x≦1.0 and 0≦y≦1.0; (BaxSr1−x)2(TayNb1−y)2O7, where 0≦x≦1.0 and 0≦y≦1.0; and (BaxSr1−x)2Bi2(TayNby−1)2O10, where 0≦x≦1.0 and 0≦y≦1.0. Thin films according to the invention have a relative dielectric constant ≧40, and preferably about 100.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: April 1, 2003
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinichiro Hayashi, Vikram Joshi, Narayan Solayappan, Joseph D. Cuchiaro, Carlos A. Paz de Araujo
  • Patent number: 6541806
    Abstract: A ferroelectric device includes a ferroelectric layer and an electrode. The ferroelectric material is made of a perovskite or a layered superlattice material. A superlattice generator metal oxide is deposited as a capping layer between said ferroelectric layer and said electrode to improve the residual polarization capacity of the ferroelectric layer.
    Type: Grant
    Filed: January 14, 1999
    Date of Patent: April 1, 2003
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinichiro Hayashi, Tatsuo Otsuki, Carlos A. Paz de Araujo
  • Patent number: 6537830
    Abstract: A nondestructive read-out, nonvolatile ferroelectric field effect transistor (“FET”) memory in an integrated circuit, containing a thin film of polycrystalline crystallographically oriented ferroelectric material. Preferably, the material is polycrystalline c-axis oriented layered superlattice material. More preferably, it is c-axis oriented strontium bismuth tantalate or strontium bismuth tantalum niobate.
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: March 25, 2003
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Arita, Carlos A. Paz de Araujo, Larry D. McMillan, Masamichi Azuma
  • Publication number: 20030052357
    Abstract: A high dielectric constant insulator including a thin film of a metal oxide selected from the group consisting of tungsten-bronze-type oxides, pyrochlore-type oxides, and combinations of Bi2O3 with an oxide selected from the group consisting of perovskites and pyrochlore-type oxides. An embodiment contains metal oxides represented by the general stoichiometric formulas AB2O6, A2B2O7 and A2Bi2B2O10, wherein A represents A-site atoms selected from the group of metals consisting of Ba, Bi, Sr, Pb, Ca, K, Na and La; and B represents B-site atoms selected from the group of metals consisting of Ti, Zr, Ta, Hf, Mo, W and Nb. Preferably, the metal oxides are (BaxSr1−x)(TayNb1−y)2O6, where 0≦y≦1.0 and 0≦y≦1.0; (BaxSr1−x)2(TayNB1−y)2O7, where 0≦x≦1.0 and 0≦y≦1.0; and (BaxSr1−x)2(TayNb1−y)2O10, where 0≦x≦1.0 and 0≦y≦1.0. Thin films according to the invention have a relative dielectric constant ≳40, and preferably about 100.
    Type: Application
    Filed: October 23, 2002
    Publication date: March 20, 2003
    Applicant: Symetrix Corporation
    Inventors: Shinichiro Hayashi, Vikram Joshi, Narayan Solayappan, Joseph D. Cuchiaro, Carlos A. Paz de Araujo
  • Publication number: 20030034548
    Abstract: A ferroelectric device includes a ferroelectric layer and an electrode. The ferroelectric material is made of a perovskite or a layered superlattice material. A superlattice generator metal oxide is deposited as a capping layer between said ferroelectric layer and said electrode to improve the residual polarization capacity of the ferroelectric layer.
    Type: Application
    Filed: September 30, 2002
    Publication date: February 20, 2003
    Applicant: Symetrix Corporation
    Inventors: Shinichiro Hayashi, Tatsuo Otsuki, Carlos A. Paz de Araujo
  • Patent number: 6512256
    Abstract: In an integrated circuit, a stack of thin film layers comprising respectively a bottom electrode, a thin film of metal oxide, a top electrode, a lower barrier-adhesion layer, a hydrogen barrier layer, and an upper barrier-adhesion layer are patterned to form a memory capacitor capped with a self-aligned hydrogen barrier layer. Preferably, the top and bottom electrodes comprise platinum, the metal oxide material comprises ferroelectric layered superlattice material, the upper and lower barrier-adhesion layers comprise titanium, and the hydrogen barrier layer comprises titanium nitride. The hydrogen barrier layer inhibits diffusion of hydrogen, thereby preventing hydrogen degradation of the metal oxides. Part of the upper barrier-adhesion layer is removed in order to increase the electrical conductivity in the layer. Preferably, the memory capacitor is a ferroelectric nonvolatile memory. Preferably, the layered superlattice material includes strontium bismuth tantalate or strontium bismuth tantalum niobate.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: January 28, 2003
    Assignees: Symetrix Corporation, NEC Corporation
    Inventors: Joseph D. Cuchiaro, Akira Furuya, Carlos A. Paz de Araujo, Yoichi Miyasaka
  • Patent number: 6511718
    Abstract: A venturi mist generator creates a mist comprising droplets having a mean diameter less than one micron from liquid precursors containing multi-metal polyalkoxide compounds. The mist is mixed and then passed into a gasifier where the mist droplets are gasified at a temperature of between 100° C. and 250° C., which is lower than the temperature at which the precursor compounds decompose. The gasified precursor compounds are transported by carrier gas through insulated tubing at ambient temperature to prevent both condensation and premature decomposition. The gasified precursors are mixed with oxidant gas, and the gaseous reactant mixture is injected through a showerhead inlet into a deposition reactor in which a substrate is heated at a temperature of from 300° C. to 600 ° C. The gasified precursors decompose at the substrate and form a thin film of solid material on the substrate. The thin film is treated at elevated temperatures of from 500° C. to 900° C.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: January 28, 2003
    Assignee: Symetrix Corporation
    Inventors: Carlos A. Paz de Araujo, Larry D. McMillan, Narayan Solayappan, Jeffrey W. Bacon
  • Patent number: 6495878
    Abstract: A high dielectric constant insulator including a thin film of a metal oxide selected from the group consisting of tungsten-bronze-type oxides, pyrochlore-type oxides, and combinations of Bi2O3 with an oxide selected from the group consisting of perovskites and pyrochlore-type oxides. An embodiment contains metal oxides represented by the general stoichiometric formulas AB2O6, A2B2O7 and A2Bi2B2O10, wherein A represents A-site atoms selected from the group of metals consisting of Ba, Bi, Sr, Pb, Ca, K, Na and La; and B represents B-site atoms selected from the group of metals consisting of Ti, Zr, Ta, Hf, Mo, W and Nb. Preferably, the metal oxides are (BaxSr1−x)(TayNb1−y)2O6, where 0≦x≦1.0 and 0≦y≦1.0; (BaxSr1−x)2(TayNb1−Y)2O7, where 0≦x≦1.0 and 0≦y≦1.0; and (BaxSr1−x)2Bi2(TayNb1−y)2O10, where 0≦x≦1.0 and 0≦y≦1.0. Thin films according to the invention have a relative dielectric constant ≧40, and preferably about 100.
    Type: Grant
    Filed: August 2, 1999
    Date of Patent: December 17, 2002
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinichiro Hayashi, Vikram Joshi, Narayan Solayappan, Joseph D. Cuchiaro, Carlos A. Paz de Araujo
  • Patent number: 6495709
    Abstract: A precursor for forming an aluminum oxide film comprises a liquid solution of an aluminum organic precursor compound in an organic solvent. In a second embodiment, the precursor comprises a suspension of aluminum oxide powder in a solution of an aluminum organic precursor compound. A precursor according to the invention is deposited on a substrate by dipping, rolling, spraying, misted deposition, spin on deposition, or chemical vapor deposition then heated to fabricate transparent aluminum oxide films. The electronic properties of the aluminum oxide films may be improved by depositing a plurality of layers of the precursor and annealing the precursor between layers.
    Type: Grant
    Filed: March 16, 2000
    Date of Patent: December 17, 2002
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Jolanta Celinska, Jeffrey W. Bacon, Akihiro Matsuda, Carlos A. Paz de Araujo
  • Publication number: 20020168785
    Abstract: A ferroelectric memory includes a plurality of memory cells each containing a ferroelectric thin film including a microscopically composite material having a ferroelectric material component and a fluxor material component, the fluxor material being a different chemical compound than the ferroelectric material. The fluxor is a material having a higher crystallization velocity than the ferroelectric material. The addition of the fluxor permits a ferroelectric thin film to be crystalized at a temperature of between 400° C. and 550° C.
    Type: Application
    Filed: May 10, 2001
    Publication date: November 14, 2002
    Applicant: Symetrix Corporation
    Inventors: Carlos A. Paz de Araujo, Vikram Joshi, Narayan Solayappan, Jolanta Celinska, Larry D. McMillan
  • Patent number: 6469334
    Abstract: A ferroelectric FET having an interface insulator layer containing ZrO2. The ferroelectric FET includes a gate oxide layer, the interface insulator layer is located on the gate oxide layer, and ferroelectric layered superlattice material is located on the interface insulator layer, The interface insulator layer has a thickness of from 15 to 25 nanometers.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: October 22, 2002
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Arita, Shinichiro Hayashi, Tatsuo Otsuki, Carlos A. Paz de Araujo
  • Patent number: 6454964
    Abstract: A liquid precursor solution for use according to a method of manufacturing metal oxide electronic components includes a polyoxyalkylated metal complex dispersed in an alkane solvent. The alkane solvent is preferably n-octane.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: September 24, 2002
    Assignee: Symetrix Corporation
    Inventors: Michael C. Scott, Carlos A. Paz De Araujo
  • Patent number: 6455327
    Abstract: In the manufacture of an integrated circuit memory capacitor, an underlying hydrogen barrier layer, either electrically nonconductive or conductive, is formed on a substrate. Then, the lower electrode layer and the ferroelectric/dielectric layer are formed and selectively etched. A nonconductive hydrogen barrier layer is formed on the dielectric layer and selectively etched. After a heat treatment in oxygen, the upper electrode layer and a conductive hydrogen barrier layer are successively deposited and selectively etched. The nonconductive hydrogen barrier layer covers the capacitor except for a part of the upper electrode, and the conductive hydrogen barrier layer covers a portion where there is no nonconductive hydrogen barrier layer. Thus, the underlying barrier layer, the nonconductive barrier layer and the conductive barrier layer together completely cover the memory capacitor. The dielectric layer comprises a ferroelectric or high-dielectric constant metal oxide.
    Type: Grant
    Filed: October 17, 2000
    Date of Patent: September 24, 2002
    Assignees: Symetrix Corporation, NEC Corporation
    Inventor: Yukihiko Maejima
  • Publication number: 20020125573
    Abstract: A hydrogen diffusion barrier in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of metal oxide material in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following nitrides: aluminum titanium nitride (Al2Ti3N6), aluminum silicon nitride (Al2Si3N6), aluminum niobium nitride (AlNb3N6), aluminum tantalum nitride (AlTa3N6), aluminum copper nitride (Al2Cu3N4), tungsten nitride (WN), and copper nitride (Cu3N2). The thin film of metal oxide is ferroelectric or high-dielectric, nonferroelectric material. Preferably, the metal oxide comprises ferroelectric layered superlattice material. Preferably, the hydrogen barrier layer is located directly over the thin film of metal oxide.
    Type: Application
    Filed: November 9, 2001
    Publication date: September 12, 2002
    Applicant: Symetrix Corporation
    Inventors: Joseph D. Cuchiaro, Carlos A. Paz de Araujo, Larry D. McMillan
  • Patent number: 6447838
    Abstract: A Ti/TiN adhesion/barrier layer is formed on a substrate and annealed. The anneal step is performed at a temperature within a good morphology range of 100° C. above a base barrier anneal temperature that depends on the thickness of said barrier layer. The base barrier anneal temperature is about 700° C. for a barrier thickness of about 1000 Å and about 800° C. for a barrier thickness of about 3000 Å. The barrier layer is 800 Å thick or thicker. A first electrode is formed, followed by a BST dielectric layer and a second electrode. A bottom electrode structure in which a barrier layer of TiN is sandwiched between two layers of platinum is also disclosed. The process and structures also produce good results with other capacitor dielectrics, including ferroelectrics such as strontium bismuth tantalate.
    Type: Grant
    Filed: October 16, 1995
    Date of Patent: September 10, 2002
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Masamichi Azuma, Eiji Fujii, Yasuhiro Uemoto, Shinichiro Hayashi, Toru Nasu, Yoshihiro Shimada, Akihiro Matsuda, Tatsuo Otsuki, Michael C. Scott, Joseph D. Cuchiaro, Carlos A. Paz de Araujo