Abstract: A ferroelectric memory including a bit line pair, a drive line parallel to and located between the bit lines, and an associated memory cell. The memory cell includes two capacitors, each capacitor connected to one of said bit lines via a transistor, and each capacitor is also connected to the drive line via a transistor. The gates of all three of the transistors are connected to a word line perpendicular to the bit lines and drive line, so that when the word line is not selected, the capacitors are completely isolated from any disturb. The bit lines may be complementary and the cell a one-bit cell, or the cell may be a two-bit cell. In the latter case, the memory includes a dummy cell identical to the above cell, in which the two dummy capacitors are complementary. A sense amplifier with three bit line inputs compares the cell bit line with a signal derived from the two dummy bit lines. The logic states of the dummy capacitors alternate in each cycle, preventing imprint and fatigue.

Abstract: A nonconductive hydrogen barrier layer is deposited on a substrate and completely covers the surface area over a memory capacitor and a MOSFET switch of an integrated circuit memory cell. A portion of an insulator layer adjacent to the bottom electrode of a memory capacitor is removed by etching to form a moat region. A nonconductive oxygen barrier layer is deposited to cover the sidewall and bottom of the moat. The nonconductive oxygen barrier layer and a conductive diffusion barrier beneath the capacitor together provide a substantially continuous diffusion barrier between the capacitor and a switch. Also, the nonconductive hydrogen barrier layer, the nonconductive oxygen barrier, and the conductive diffusion barrier substantially completely envelop the capacitor, in particular a ferroelectric thin film in the capacitor.

Abstract: A precursor for forming a thin film of layered superlattice material is applied to an integrated circuit substrate. The precursor coating is heated using rapid thermal processing (RTP) with a ramping rate of 100° C./second at a hold temperature in a range of from 500° C. to 900° C. for a cumulative heating time not exceeding 30 minutes, and preferably less than 5 minutes. In fabricating a ferroelectric memory cell, the coating is heated in oxygen using RTP, then a top electrode layer is formed, and then the substrate including the coating is heated using RTP in oxygen or in nonreactive gas after forming the top electrode layer. The thin film of layered superlattice material preferably comprises strontium bismuth tantalate or strontium bismuth tantalum niobate, and preferably has a thickness in a range of from 25 nm to 120 nm. The process of fabricating a thin film of layered superlattice material typically has a thermal budget value not exceeding 960,000° C.

Abstract: A nonconductive hydrogen barrier layer completely covers the surface area over a memory capacitor and a MOSFET switch of an integrated circuit memory cell. The nonconductive hydrogen barrier layer and a conductive diffusion barrier beneath the capacitor together provide a continuous diffusion barrier between the capacitor and a switch. Also, the nonconductive hydrogen barrier layer and the conductive diffusion barrier continuously envelop the capacitor, in particular a ferroelectric thin film in the capacitor. Preferably, a nonconductive “buried” diffusion barrier layer is disposed over an extended area, providing a continuous diffusion barrier between the capacitor and the switch. A preferred fabrication method comprises forming a thin stack-electrode layer on a capacitor dielectric layer, and then etching the substrate to form self-aligning capacitor stacks.

Abstract: Integrated circuit capacitors in which the capacitor dielectric is a thin film of BST having a grain size smaller than 200 nanometers formed above a silicon germanium substrate. Typical grain sizes are 40 nm and less. The BST is formed by deposition of a liquid precursor by a spin-on process. The original liquid precursor includes an alkoxycarboxylate dissolved in 2-methoxyethanol and a xylene exchange is performed just prior to spinning. The precursor is dried in air at a temperature of about 400° C. and then furnace annealed in oxygen at a temperature of between 600° C. and 850° C.

Abstract: A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.

Abstract: A nonconductive hydrogen barrier layer is deposited on a substrate and completely covers the surface area over a memory capacitor and a MOSFET switch of an integrated circuit memory cell. A portion of an insulator layer adjacent to the bottom electrode of a memory capacitor is removed by etching to form a moat region. A nonconductive oxygen barrier layer is deposited to cover the sidewall and bottom of the moat. The nonconductive oxygen barrier layer and a conductive diffusion barrier beneath the capacitor together provide a substantially continuous diffusion barrier between the capacitor and a switch. Also, the nonconductive hydrogen barrier layer, the nonconductive oxygen barrier, and the conductive diffusion barrier substantially completely envelop the capacitor, in particular a ferroelectric thin film in the capacitor.

Abstract: A liquid precursor for forming a transparent metal oxide thin film comprises a first organic precursor compound. In one embodiment, the liquid precursor is for making a conductive thin film. In this embodiment, the liquid precursor contains a first metal from the group including tin, antimony, and indium dissolved in an organic solvent. The liquid precursor preferably comprises a second organic precursor compound containing a second metal from the same group. Also, the liquid precursor preferably comprises an organic dopant precursor compound containing a metal selected from the group including niobium, tantalum, bismuth, cerium, yttrium, titanium, zirconium, hafnium, silicon, aluminum, zinc and magnesium. Liquid precursors containing a plurality of metals have a longer shelf life. The addition of an organic dopant precursor compound containing a metal, such as niobium, tantalum or bismuth, to the liquid precursor enhances control of the conductivity of the resulting transparent conductor.

Abstract: An MIS device (20) includes a semiconducting substrate (22), a silicon nitride buffer layer (24), a ferroelectric metal oxide superlattice material (26), and a noble metal top electrode (28). The layered superlattice material (26) is preferably a strontium bismuth tantalate, strontium bismuth niobate, or strontium bismuth niobium tantalate. The device is constructed according to a preferred method that includes forming the silicon nitride on the semiconducting substrate prior to deposition of the layered superlattice material. The layered superlattice material is preferably deposited using liquid polyoxyalkylated metal organic precursors that spontaneously generate a layered superlattice upon heating of the precursor solution. UV exposure during drying of the precursor liquid imparts a taxis orientation to the final crystal, and results in improved thin-film electrical properties.

Abstract: A ferroelectric thin film precursor material is annealed while in an electric field. The electric field is maintained as the material cools. A partially completed integrated circuit with a ferroelectric thin film precursor material may be placed between two electrodes in an annealing apparatus and voltage sufficient to polarize the ferroelectric thin film material in the direction of the electrical field is supplied to the electrodes during the anneal and as the film cools. Alternatively, probes are connected to the electrodes of a partially completed integrated circuit device and voltage sufficient to polarize the ferroelectric material is applied while annealing the material and as it cools. The anneal may be a furnace anneal or an RTP anneal.

Abstract: A ferroelectric device includes a ferroelectric layer and an electrode. The ferroelectric material is made of a perovskite or a layered superlattice material. A superlattice generator metal oxide is deposited as a capping layer between said ferroelectric layer and said electrode to improve the residual polarization capacity of the ferroelectric layer.

Abstract: An MIS device (20) includes a semiconducting substrate (22), a silicon nitride buffer layer (24), a ferroelectric metal oxide superlattice material (26), and a noble metal top electrode (28). The layered superlattice material (26) is preferably a strontium bismuth tantalate, strontium bismuth niobate, or strontium bismuth niobium tantalate. The device is constructed according to a preferred method that includes forming the silicon nitride on the semiconducting substrate prior to deposition of the layered superlattice material. The layered superlattice material is preferably deposited using liquid polyoxyalkylated metal organic precursors that spontaneously generate a layered superlattice upon heating of the precursor solution. UV exposure during drying of the precursor liquid imparts a C-axis orientation to the final crystal, and results in improved thin-film electrical properties.

Abstract: A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.

Abstract: Integrated circuit capacitors in which the capacitor dielectric is a thin film of BST having a grain size smaller than 200 nanometers formed above a silicon germanium substrate. Typical grain sizes are 40 nm and less. The BST is formed by deposition of a liquid precursor by a spin-on process. The original liquid precursor includes an alkoxycarboxylate dissolved in 2-methoxyethanol and a xylene exchange is performed just prior to spinning. The precursor is dried in air at a temperature of about 400° C. and then furnace annealed in oxygen at a temperature of between 600° C. and 850° C.

Abstract: A ferroelectric thin film precursor material is annealed while in an electric field. The electric field is maintained as the material cools. A partially completed integrated circuit with a ferroelectric thin film precursor material may be placed between two electrodes in an annealing apparatus and voltage sufficient to polarize the ferroelectric thin film material in the direction of the electrical field is supplied to the electrodes during the anneal and as the film cools. Alternatively, probes are connected to the electrodes of a partially completed integrated circuit device and voltage sufficient to polarize the ferroelectric material is applied while annealing the material and as it cools. The anneal may be a furnace anneal or an RTP anneal.

Abstract: A liquid precursor for forming a layered superlattice material is applied to an integrated circuit substrate. The precursor coating is annealed in oxygen using a rapid temperature pulsing anneal (“RPA”) technique with a ramp rate of 30° C./second at a hold temperature of 650° C. for a holding time of 30 minutes. The RPA technique includes applying a plurality of rapid-temperature heat pulses in sequence.

Abstract: An integrated circuit includes a layered superlattice material including one or more of the elements cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium. These elements may either be A-site elements or superlattice generator elements in the layered superlattice material. In one embodiment, one or more of these elements substitute for bismuth in a bismuth layered material. They also are preferably used in combination with one or more of the following elements: strontium, calcium, barium, bismuth, cadmium, lead, titanium, tantalum, hafnium, tungsten, niobium, zirconium, bismuth, scandium, yttrium, lanthanum, antimony, chromium, thallium, oxygen, chlorine, and fluorine. Some of these materials are ferroelectrics that crystallize at relatively low temperatures and are applied in ferroelectric non-volatile memories.

Abstract: A nonconductive hydrogen barrier layer is deposited on a substrate and completely covers the surface area over a memory capacitor and a MOSFET switch of an integrated circuit memory cell. A portion of an insulator layer adjacent to the bottom electrode of a memory capacitor is removed by etching to form a moat region. A nonconductive oxygen barrier layer is deposited to cover the sidewall and bottom of the moat. The nonconductive oxygen barrier layer and a conductive diffusion barrier beneath the capacitor together provide a substantially continuous diffusion barrier between the capacitor and a switch. Also, the nonconductive hydrogen barrier layer, the nonconductive oxygen barrier, and the conductive diffusion barrier substantially completely envelop the capacitor, in particular a ferroelectric thin film in the capacitor.

Abstract: A thin film of precursor for forming a layered superlattice material is applied to an integrated circuit substrate, then a strong oxidizing agent is applied at low temperature in a range of from 100° C. to 300° C. to the precursor thin film, thereby forming a metal oxide thin film. The strong oxidizing agent may be liquid or gaseous. An example of a liquid strong oxidizing agent is hydrogen peroxide. An example of a gaseous strong oxidizing agent is ozone. The metal oxide thin film is crystallized by annealing at elevated temperature in a range of from 500° C. to 700° C., preferably not exceeding 650° C., for a time period in a range of from 30 minutes to two hours. Annealing is conducted in an oxygen-containing atmosphere, preferably including water vapor. Treatment by ultraviolet (UV) radiation may precede annealing. RTP in a range of from 500° C. to 700° C. may precede annealing.

Abstract: A nonconductive hydrogen barrier layer completely covers the surface area over a memory capacitor and a MOSFET switch of an integrated circuit memory cell. The nonconductive hydrogen barrier layer and a conductive diffusion barrier beneath the capacitor together provide a continuous diffusion barrier between the capacitor and a switch. Also, the nonconductive hydrogen barrier layer and the conductive diffusion barrier continuously envelop the capacitor, in particular a ferroelectric thin film in the capacitor. Preferably, a nonconductive “buried” diffusion barrier layer is disposed over an extended area, providing a continuous diffusion barrier between the capacitor and the switch. A preferred fabrication method comprises forming a thin stack-electrode layer on a capacitor dielectric layer, and then etching the substrate to form self-aligning capacitor stacks.