Patents Assigned to Symetrix Corporation
  • Patent number: 6448190
    Abstract: A thin film of solid material is selectively formed during fabrication of an integrated circuit by applying a liquid precursor to a substrate having a first surface and a second surface and treating the liquid precursor. The first surface has different physical properties than the second surface such that a solid thin film forms on the first surface but does not form on the second surface. The substrate is washed after formation of said solid thin film to remove any residues of said liquid from the second substrate surface.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: September 10, 2002
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinichiro Hayashi, Larry D. McMillan, Carlos A. Paz de Araujo
  • Patent number: 6441414
    Abstract: A ferroelectric non-volatile memory in which each memory cell consists of a single electronic element, a ferroelectric FET. The FET includes a source, drain, gate and substrate. The fact that the drain to source current, lds, is always negative if a substrate to drain bias, Vss, of 0.8 volts or more is applied, permits the creation of a read and write truth table. A gate voltage equal to one truth table logic value is applied via a column decoder and a substrate bias equal to another truth table logic value is applied via a row decoder to write to the memory a resultant lds logic state, which can be read whenever a voltage is placed across the source and drain.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: August 27, 2002
    Assignee: Symetrix Corporation
    Inventors: Myoungho Lim, Vikram Joshi, Jeffrey W. Bacon, Joseph D. Cuchiaro, Larry D. McMillan, Carlos A. Paz de Araujo
  • Patent number: 6437380
    Abstract: An integrated circuit device includes a thin film of bismuth-containing layered superlattice material having a thickness not exceeding 100 nm, a capping layer thin film of bismuth tantalate, and an electrode. The capping layer has a thickness in a range of from 3 nm to 30 nm and is deposited between the thin film of layered superlattice material and the electrode to increase dielectric breakdown voltage. Preferably the capping layer contains an excess amount of bismuth relative to the stoichiometrically balanced amount represented by the balanced stoichiometric formula BiTaO4. Preferably, the layered superlattice material is ferroelectric SBT or SBTN. Preferably, the integrated circuit device is a nonvolatile ferroelectric memory. Heating treatments for fabrication of the integrated circuit device containing the bismuth tantalate capping layerare conducted at temperatures not exceeding 700° C., preferably in a range of from 650° C. to 700° C.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: August 20, 2002
    Assignee: Symetrix Corporation
    Inventors: Myoungho Lim, Vikram Joshi, Narayan Solayappan, Larry D. McMillan, Carlos A. Paz de Araujo
  • Publication number: 20020109178
    Abstract: An integrated circuit capacitor containing a thin film of dielectric metal oxide is formed above a silicon germanium substrate. A silicon nitride diffusion barrier layer is deposited on a silicon germanium substrate to prevent evaporation of the substrate in subsequent heating steps. A silicon dioxide stress reduction layer is deposited on the diffusion barrier layer. A bottom electrode is formed on the stress reduction layer, then a liquid precursor is spun on the bottom electrode, dried at about 400° C., and annealed at between 600° C. and 850° C. to form a BST capacitor dielectric. A top electrode is deposited on the dielectric and annealed. The integrated circuit may also include a BiCMOS device, a HBT device or a MOSFET.
    Type: Application
    Filed: April 10, 2002
    Publication date: August 15, 2002
    Applicant: Symetrix Corporation
    Inventors: Larry D. McMillan, Carlos A. Paz de Araujo, Koji Arita, Masamichi Azuma
  • Publication number: 20020092472
    Abstract: A plurality of liquids, the flow of each controlled by a volumetric flowrate controller, are mixed in a mixer to form a final precursor that is misted and then deposited on a substrate. A physical property of precursor liquid is adjusted by adjusting the volumetric flowrate controllers, so that when precursor is applied to substrate and treated, the resulting thin film of solid material has a smooth and planar surface. Typically the physical property is the viscosity of the precursor, which is selected to be relatively low, in the range of 1-2 centipoise.
    Type: Application
    Filed: March 12, 2002
    Publication date: July 18, 2002
    Applicant: Symetrix Corporation and Matsushita Electronics Corporation
    Inventors: Shinichiro Hayashi, Larry D. McMillan, Carlos A. Paz de Araujo
  • Publication number: 20020087018
    Abstract: A liquid precursor for forming a transparent metal oxide thin film comprises a first organic precursor compound. In one embodiment, the liquid precursor is for making a conductive thin film. In this embodiment, the liquid precursor contains a first metal from the group including tin, antimony, and indium dissolved in an organic solvent. The liquid precursor preferably comprises a second organic precursor compound containing a second metal from the same group. Also, the liquid precursor preferably comprises an organic dopant precursor compound containing a metal selected from the group including niobium, tantalum, bismuth, cerium, yttrium, titanium, zirconium, hafnium, silicon, aluminum, zinc and magnesium. Liquid precursors containing a plurality of metals have a longer shelf life. The addition of an organic dopant precursor compound containing a metal, such as niobium, tantalum or bismuth, to the liquid precursor enhances control of the conductivity of the resulting transparent conductor.
    Type: Application
    Filed: November 9, 2001
    Publication date: July 4, 2002
    Applicant: Symetrix Corporation
    Inventors: Jolanta Celinska, Carlos A. Paz de Araujo, Joseph D. Cuchiaro, Jeffrey W. Bacon, Larry D. McMillan
  • Patent number: 6413883
    Abstract: A plurality of liquids, the flow of each controlled by a volumetric flowrate controller, are mixed in a mixer to form a final precursor that is misted and then deposited on a substrate. A physical property of precursor liquid is adjusted by adjusting the volumetric flowrate controllers, so that when precursor is applied to substrate and treated, the resulting thin film of solid material has a smooth and planar surface. Typically the physical property is the viscosity of the precursor, which is selected to be relatively low, in the range of 1-2 centipoise.
    Type: Grant
    Filed: February 3, 1999
    Date of Patent: July 2, 2002
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinichiro Hayashi, Larry D. McMillan, Carlos A. Paz de Araujo
  • Patent number: 6404003
    Abstract: An integrated circuit capacitor containing a thin film delectric metal oxide is formed above a silicon germanium substrate. A silicon nitride diffusion barrier layer is deposited on a silicon germanium substrate to prevent evaporation of the substrate in subsequent heating steps. A silicon dioxide stress reduction layer is deposited on the diffusion barrier layer. A bottom electrode is formed on the stress reduction layer, then a liquid precursor is spun on the bottom electrode, dried at about 400° C., and annealed at between 600° C. and 850° C. to form a BST capacitor dielectric. A top electrode is deposited on the dielectric and annealed. The integrated circuit may also include a BiCMOS device, a HBT device or a MOSFET.
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: June 11, 2002
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Larry D. McMillan, Carlos A. Paz de Araujo, Koji Arita, Masamichi Azuma
  • Patent number: 6395612
    Abstract: A semiconductor device has a device isolation oxide film, an interlayer insulating film, hydrogen barrier films, a lower electrode, a capacitor insulating film, an upper electrode, an interlayer insulating film and a wiring layer, formed on a silicon substrate. A gate electrode is formed on a gate oxide film between impurity diffusion regions in the silicon substrate. Further, a capacitor portion, comprising the lower electrode, the capacitor insulating film (ferroelectric or high dielectric substance) and the upper electrode, is completely covered with the hydrogen barrier films. The hydrogen barrier films prevent deterioration of the ferroelectric substance and the high dielectric constant material due to reducing conditions in a hydrogen atmosphere. Other device characteristics, however, are not adversely affected because only the capacitor portion is completely covered with the hydrogen barrier films.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: May 28, 2002
    Assignees: Symetrix Corporation, NEC Corporation
    Inventor: Kazushi Amanuma
  • Patent number: 6383555
    Abstract: A substrate is located within a deposition chamber, the substrate defining a substrate plane. A liquid precursor is misted by ultrasonic or venturi apparatus, to produce a colloidal mist. The mist is generated, allowed to settle in a buffer chamber, filtered through a system up to 0.01 micron, and flowed into the deposition chamber between the substrate and barrier plate to deposit a liquid layer on the substrate. The liquid is dried to form a thin film of solid material on the substrate, which is then incorporated into an electrical component of an integrated circuit.
    Type: Grant
    Filed: July 13, 2000
    Date of Patent: May 7, 2002
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinichiro Hayashi, Larry D. McMillan, Carlos A. Paz de Araujo
  • Patent number: 6376691
    Abstract: A liquid precursor for forming a transparent metal oxide thin film comprises a first organic precursor compound. In one embodiment, the liquid precursor is for making a conductive thin film. In this embodiment, the liquid precursor contains a first metal from the group including tin, antimony, and indium dissolved in an organic solvent. The liquid precursor preferably comprises a second organic precursor compound containing a second metal from the same group. Also, the liquid precursor preferably comprises an organic dopant precursor compound containing a metal selected from the group including niobium, tantalum, bismuth, cerium, yttrium, titanium, zirconium, hafnium, silicon, aluminum, zinc and magnesium. Liquid precursors containing a plurality of metals have a longer shelf life. The addition of an organic dopant precursor compound containing a metal, such as niobium, tantalum or bismuth, to the liquid precursor enhances control of the conductivity of the resulting transparent conductor.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: April 23, 2002
    Assignee: Symetrix Corporation
    Inventors: Jolanta Celinska, Carlos A. Paz de Araujo, Joseph D. Cuchiaro, Jeffrey W. Bacon, Larry D. McMillan
  • Patent number: 6372286
    Abstract: Integrated circuit capacitors in which the capacitor dielectric is a thin film of BST having a grain size smaller than 2000 Å. Typical gain sizes are 40 nanometers and less. The BST is formed by deposition of a liquid precursor by a spin-on process. The original liquid precursor includes an alkoxycarboxylate dissolved in 2-methoxyethanol and an xylene exchange is preformed just prior to spinning. The precursor is dried in air at a temperature of about 400° C. and then furnace annealed in oxygen at a temperature of between 675° C. and 850° C.
    Type: Grant
    Filed: July 19, 1994
    Date of Patent: April 16, 2002
    Assignees: Symetrix Corporation, Matsushita Electrical Industrial Co., Ltd.
    Inventors: Masamichi Azuma, Michael C. Scott, Carlos A. Paz de Araujo, Joseph D. Cuchiaro
  • Patent number: 6373743
    Abstract: A ferroelectric non-volatile memory comprising: a plurality of memory cells each containing a ferroelectric FET, each of said ferroelectric FETs having a source, a drain, a substrate, and a gate. The FETs are arranged in an array comprising a plurality of rows and a plurality of columns. There are a plurality of row select lines, each associated with one of the rows of said ferroelectric FETs, and a plurality of column select lines, each associated with one of the columns of ferroelectric FETs. Each of the sources is directly electrically connected to its associated row select line, and each of the drains is directly electrically connected to its associated column select line. The source and substrate of each FET are also directly electrically connected. A memory cell is read by connecting its row select line to ground, and its column select line to a small voltage. All the gates, and the row select lines of non-selected cells are open or connected to a high resistance source.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: April 16, 2002
    Assignee: Symetrix Corporation
    Inventors: Zheng Chen, Myoungho Lim, Vikram Joshi, Carlos A. Paz de Araujo, Larry D. McMillan
  • Patent number: 6370056
    Abstract: A ferroelectric non-volatile memory comprising: a plurality of memory cells, each containing an FeFET and a MOSFET, each of said FeFETs having a source, a drain, a substrate, and a gate, and each MOSFET having a pair of source/drains and a gate. The cells are arranged in an array comprising a plurality of rows and a plurality of columns. A gate line and a bit line are associated with each column, and a word line, a drain line, and a substrate line are associated with each row. One source/drain of each MOSFET is connected to its corresponding gate line; the other source/drain is connected to the gate of the FeFET in the cell. The gate of the MOSFET is connected to its corresponding word line which provides a write and erase enable signal. The drain of the FeFET is connected to its corresponding drain line, and the source of the FeFET is connected to its corresponding bit line. The substrate of each FeFET is connected to its corresponding substrate line.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: April 9, 2002
    Assignee: Symetrix Corporation
    Inventors: Zheng Chen, Vikram Joshi, Myoungho Lim, Carlos A. Paz de Araujo, Larry D. McMillan
  • Patent number: 6365927
    Abstract: A hydrogen diffusion barrier in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of metal oxide material in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following nitrides: aluminum titanium nitride (Al2Ti3N6), aluminum silicon nitride (Al2Si3N6), aluminum niobium nitride (AlNb3N6), aluminum tantalum nitride (AlTa3N6), aluminum copper nitride (Al2Cu3N4), tungsten nitride (WN), and copper nitride (Cu3N2). The thin film of metal oxide is ferroelectric or high-dielectric, nonferroelectric material. Preferably, the metal oxide comprises ferroelectric layered superlattice material. Preferably, the hydrogen barrier layer is located directly over the thin film of metal oxide.
    Type: Grant
    Filed: April 3, 2000
    Date of Patent: April 2, 2002
    Assignee: Symetrix Corporation
    Inventors: Joseph D. Cuchiaro, Carlos A. Paz de Araujo, Larry D. McMillan
  • Patent number: 6358758
    Abstract: A liquid precursor for forming a thin film of ferroelectric metal oxide in an integrated circuit contains metal oxides in excess of the stoichiometrically balanced amount. When the precursor comprises strontium, bismuth, tantalum and niobium for forming strontium bismuth tantalum niobate, the precursor contains excess amounts of at least one of tantalum and niobium. Capacitors containing thin films of layered superlattice material made from a precursor containing excess tantalum and niobium show good polarizability and low percentage imprint after 1010 negative polarization switching pulses at 75° C., and after 109 negative polarization switching pulses at 125° C.
    Type: Grant
    Filed: May 19, 2001
    Date of Patent: March 19, 2002
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Arita, Shinichiro Hayashi, Joseph D. Cuchiaro, Carlos A. Paz de Araujo
  • Patent number: 6339238
    Abstract: A ferroelectric non-volatile memory in which each memory cell consists of a single electronic element, a ferroelectric FET. The FET includes a source, drain, gate and substrate. A cell is selected for writing or reading by application of bias voltages to the source, drain, gate or substrate. A gate voltage equal to one truth table logic value and a drain voltage equal to another truth table logic value are applied via a row decoder, and a substrate bias equal to a third truth table logic value is applied via a column decoder to write to the memory a resultant Ids logic state, which can be non-destructively read by placing a voltage across the source and drain.
    Type: Grant
    Filed: June 10, 1999
    Date of Patent: January 15, 2002
    Assignee: Symetrix Corporation
    Inventors: Myoungho Lim, Vikram Joshi, Joseph D. Cuchiaro, Larry D. McMillan, Carlos A. Paz de Araujo
  • Publication number: 20010054728
    Abstract: Integrated circuit capacitors in which the capacitor dielectric is a thin film of BST having a grain size smaller than 200 nanometers formed above a silicon germanium substrate. Typical grain sizes are 40 nm and less. The BST is formed by deposition of a liquid precursor by a spin-on process. The original liquid precursor includes an alkoxycarboxylate dissolved in 2-methoxyethanol and a xylene exchange is performed just prior to spinning. The precursor is dried in air at a temperature of about 400° C. and then furnace annealed in oxygen at a temperature of between 600° C. and 850° C.
    Type: Application
    Filed: July 16, 2001
    Publication date: December 27, 2001
    Applicant: Symetrix Corporation
    Inventors: Carlos A. Paz de Araujo, Masamichi Azuma, Larry D. McMillan, Koji Arita
  • Patent number: 6326315
    Abstract: A liquid precursor for forming a layered superlattice material is applied to an integrated circuit substrate. The precursor coating is annealed in oxygen using a rapid ramping anneal (“RRA”) technique with a ramping rate of 50° C./second at a hold temperature of 650° C. for a holding time of 30 minutes.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: December 4, 2001
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Kiyoshi Uchiyama, Koji Arita, Narayan Solayappan, Carlos A. Paz de Araujo
  • Patent number: 6322849
    Abstract: An integrated circuit is formed containing a metal-oxide ferroelectric thin film. An inert-gas recovery anneal is conducted to reverse the degradation of ferroelectric properties caused by hydrogen. The inert-gas recovery anneal is conducted in an unreactive gas atmosphere at a temperature range from 300° to 1000° C. for a time period from one minute to two hours. Preferably, the metal-oxide thin film comprises layered superlattice material. Preferably, the layered superlattice material comprises strontium bismuth tantalate or strontium bismuth tantalum niobate. If the integrated circuit manufacture includes a forming-gas anneal, then the inert-gas recovery anneal is performed after the forming-gas anneal, preferably at or near the same temperature and for the same time duration as the forming-gas anneal.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: November 27, 2001
    Assignees: Symetrix Corporation, Spemens AG
    Inventors: Vikram Joshi, Narayan Solayappan, Walter Hartner, Günther Schindler