Patents Assigned to Synaptics Japan GK
  • Patent number: 10522068
    Abstract: Techniques for displaying a quality-improved image with reduced power consumption are provided. In one embodiment, a display panel driver is provided that includes a dithering section configured to receive first m-bit image data and configured to generate second image data by performing dithering on the first image data with n-bit dither values each selected from elements of a dither table, and a driver circuit configured to drive the source lines of a display panel in response to the second image data. In generating the second image data corresponding to first pixels belonging to a first pixel column, the dither values are selected from elements in a first column of the dither table, while the second image data corresponding to second pixels belonging to a second pixel column adjacent to the first pixel column, the dither values are selected from elements in a second column of the dither table.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: December 31, 2019
    Assignee: Synaptics Japan GK
    Inventors: Hirobumi Furihata, Takashi Nose
  • Patent number: 10522067
    Abstract: A display panel driver includes an image data generator, a brightness correction circuit performing a correction calculation on image data, a drive section driving the display panel in response to corrected image data; and a display timing generator outputting a timing control signal. The correction calculation by the brightness correction circuit is adjustable. When the display panel driver is placed into a test mode, the display timing generator is configured to output an internally-generated timing control signal and the image data generator outputs internally-generated evaluation image data. The evaluation image data are generated so that the evaluation images are switched from one to another in response to the internally-generated timing control signal.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: December 31, 2019
    Assignee: Synaptics Japan GK
    Inventors: Akio Sugiyama, Takashi Nose, Hirobumi Furihata
  • Patent number: 10509508
    Abstract: Provided is a touch sensing circuit configured to sense an approach of a conductive object toward a sensor capacitor through measuring a sensor response signal generated by the sensor capacitor in response to a sensing wave signal applied to the sensor capacitor. The touch sensing circuit is connectable to a conversion circuit and a touch detection circuit. The conversion circuit calculates a response signal vector for a frequency component of the sensing wave signal by converting the response signal into a frequency domain representation. The touch sensing circuit includes a baseline vector manager circuit holding a baseline vector and a vector subtraction circuit, and calculates a delta vector which is the vector difference between the baseline vector and the response signal vector received from the conversion circuit. The touch detection circuit detects an approach of a conductive object towards the sensor capacitor on the basis of the calculated delta vector.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: December 17, 2019
    Assignee: Synaptics Japan GK
    Inventors: Nobukazu Tanaka, Takayuki Noto, Tetsuo Tanemura
  • Patent number: 10510138
    Abstract: A display panel driver includes a scaler circuit performing image enlargement processing on input image data corresponding to an input image to generate ?-times enlarged image data corresponding to an ?-times enlarged image (? is a number larger than one which cannot be represented as 2k); and a driver section driving a display panel. In calculating a pixel value of a target pixel of the ?-times enlarged image, the scaler circuit generates enlarged image data including 2n-times enlarged image data corresponding to a 2n-times enlarged image obtained by enlarging the input image with an enlargement factor of 2n (n is the smallest integer determined so that 2n is larger than ?), and calculates the pixel value of the target pixel from the 2n-times enlarged image data through interpolation processing of pixel values of pixels of the 2n-times enlarged image corresponding to the target pixel of the ?-times enlarged image.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: December 17, 2019
    Assignee: Synaptics Japan GK
    Inventors: Hirobumi Furihata, Takashi Nose, Masao Orio
  • Patent number: 10504478
    Abstract: A semiconductor device has a first mode in which the semiconductor device is used alone and a second mode in which the semiconductor device is used in combination with another semiconductor device. In case that one driven device is driven using the semiconductor device in the first mode and the second mode, power supply lines are caused to allow electrical conduction to each other outside of each semiconductor device in order to cancel errors of operation power supply voltages of each semiconductor device. In case that a power supply unit of each semiconductor device is operable by receiving an instruction for release of a low power consumption state, a supply start timing of the operation power supply voltages in the second mode is delayed as compared to that in the first mode.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: December 10, 2019
    Assignee: Synaptics Japan GK
    Inventors: Noriyuki Ishii, Atsushi Shikata
  • Patent number: 10503336
    Abstract: A semiconductor device includes an analog front end and processing circuitry. The analog front end is configured to obtain capacitance detection data depending on capacitances of a plurality of sense electrodes of a liquid crystal display panel. The processing circuitry is configured to generate touch sensing data associated with a current touch sensing frame, based on capacitance detection data associated with the current touch sensing frame and capacitance detection data associated with a former touch sensing frame selected in response to a state in which the liquid crystal display panel is placed in the current touch sensing frame.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: December 10, 2019
    Assignee: Synaptics Japan GK
    Inventors: Nobukazu Tanaka, Takayuki Noto, Yoshitaka Iwasaki
  • Patent number: 10446111
    Abstract: An image data transfer system includes a receiver and a transmitter configured to sequentially receive compressed image data and sequentially transmit transmission data corresponding to the compressed image data to the receiver. The transmitter is configured to, in transmitting a specific transmission data, perform data comparison of bits of a compressed image body data of a specific compressed image data with bits of a previous transmission data transmitted over signal lines allocated to the compressed image body data, incorporate the compressed image body data of the specific compressed image data or the bit-inverted data corresponding thereto into the specific transmission data, in response to the result of the data comparison, and incorporate the compression code of the specific compressed image data into the specific transmission data independently of the result of the data comparison.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: October 15, 2019
    Assignee: Synaptics Japan GK
    Inventors: Hirobumi Furihata, Masashige Harada, Iori Shiraishi, Takashi Nose
  • Patent number: 10402023
    Abstract: Provided is a technique which enables the avoidance of a temporal damage to a panel module, and keeps a voltage load on a display panel circuit node from becoming excessively large even if a constant voltage is applied to the node for a longer time exceeding a display drive term in a non-display drive term, provided that a display frame period is divided to have display and non-display drive terms. In performing display and touch-sensing actions on condition that a display frame period is divided to include display and non-display drive terms, an operation source voltage supplied to a panel module during the non-display term where touch sensing is performed is smaller, in absolute value, than that supplied in the display term, whereby a voltage load applied to an input circuit node of a panel module for a longer time exceeding the display term is kept from being excessively large.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: September 3, 2019
    Assignee: Synaptics Japan GK
    Inventor: Tsuyoshi Kuroiwa
  • Patent number: 10388210
    Abstract: A system and method for driving horizontal lines comprising detecting one or more errors within display data corresponding to one or more of the horizontal lines and generating second display data for a first horizontal line when the first display data for the first horizontal line is determined to include a data error, wherein the second display data is based on the first display data for a second horizontal line of the plurality of horizontal lines.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: August 20, 2019
    Assignee: Synaptics Japan GK
    Inventor: Tsuyoshi Kuroiwa
  • Patent number: 10380936
    Abstract: A display panel driver includes: a correction calculation section which performs correction calculations on input image data to generate saturation-enhanced output image data and a drive circuitry driving the display panel in response to the output image data and a starting point control section. The correction calculation section generates red (R) data, green (G) data and blue (B) data of the output image data by performing the correction calculations on R data, G data and B data of the input image data, respectively. The starting point control section controls the positions of starting points of the input-output curves of the correction calculations.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: August 13, 2019
    Assignee: Synaptics Japan GK
    Inventors: Takashi Nose, Hirobumi Furihata, Akio Sugiyama
  • Patent number: 10373862
    Abstract: Provided is a semiconductor device including an active region defined by a separation region on a main surface of a semiconductor substrate, and a field effect transistor formed in the active region. A boundary portion, over which a gate electrode pattern strides, is disposed in a boundary between the active region and the separation region and is configured such that a length of one side, in a direction of a gate length of the field effect transistor formed in the active region, becomes larger than the gate length and does not come into contact with at least one of a pair of source and drain regions of the field effect transistor.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: August 6, 2019
    Assignee: Synaptics Japan GK
    Inventor: Masatoshi Taya
  • Patent number: 10373584
    Abstract: A color adjustment circuit includes: a correction processing circuit configured to generate an output image data by performing color adjustment correction on an input image data; and a correction factor calculation circuit configured to calculate correction factors used for the color adjustment correction. The correction factor calculation circuit calculates a white color distance, a complementary color distance, and an elementary color distance and calculates the correction factors based on the white color distance, the complementary color distance and the elementary color distance. The correction factors are calculated based on: white point correction parameters, top correction parameters, and intermediate correction parameters.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: August 6, 2019
    Assignee: SYNAPTICS JAPAN GK
    Inventors: Masao Orio, Hirobumi Furihata, Susumu Saito, Takashi Nose, Akio Sugiyama
  • Patent number: 10332437
    Abstract: Provided is a color adjustment method for a display apparatus. The color adjustment method includes: measuring first luminance coordinate data indicating a luminance and color coordinates of a color displayed on a display device when image data corresponding to a white point is supplied to a drive circuitry; measuring second luminance coordinate data indicating luminances and color coordinates of colors displayed on the display device when image data corresponding to the white color of intermediate grayscale values are supplied to the drive circuitry; measuring third luminance coordinate data indicating a luminance and color coordinates of a color displayed on the display device for each of R, G and B elementary color points when image data corresponding to each of the R, G and B elementary color points is supplied to the drive circuitry; and calculating correction parameters based on the first to third luminance coordinate data.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: June 25, 2019
    Assignee: Synaptics Japan GK
    Inventors: Masao Orio, Hirobumi Furihata, Susumu Saito, Takashi Nose, Akio Sugiyama
  • Patent number: 10332442
    Abstract: Provided is a display driver which can be used in common in any of COF mounting and COG mounting. In the display driver, a position (or write/output position) of display data output by an output circuit can be changed along a direction of an array of external output terminals S1 to S540 according to mode data, whereby an array of external output terminals to use for output can be selected from more than one kind of arrays different in layout pitch. Therefore, the display driver can be used in display panels with signals lines having different pitches serving to receive drive signals from the display driver and in addition, used in common in any of COF mounting and COG mounting which are different from each other in the pitch of mounting wiring lines.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: June 25, 2019
    Assignee: Synaptics Japan GK
    Inventors: Goro Sakamaki, Kei Miyazawa
  • Patent number: 10326402
    Abstract: A circuit includes: an oscillator configured to generate an oscillation clock signal; an NMOS transistor having a source connected with a power terminal of the oscillator, and a drain connected with a first power supply line to which a first power supply voltage is supplied; an operational amplifier configured to control a gate voltage of the NMOS transistor based on a voltage of the power terminal of the oscillator; and a charge pump. The charge pump is configured to use the oscillation clock signal or a clock signal generated from the oscillation clock signal to boost the first power supply voltage and generate a boosted power supply voltage, and to supply the boosted power supply voltage to the power terminal of the operational amplifier.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: June 18, 2019
    Assignee: Synaptics Japan GK
    Inventor: Naoji Shimizu
  • Patent number: 10318052
    Abstract: A display control and touch detection device is capable of controlling display and non-display terms in start timing depending on a result of touch detection, and includes a nonvolatile memory and a control logic which selectively uses data stored in the memory according to a display mode. The control logic changes the display and non-display terms in start timing in display frame periods, whereby the phenomenon of appearance of an undesired brightness difference at a fixed location in a display frame with no display, and the phenomenon of occurrence of flicker owing to the undesired brightness difference can be suppressed. Based on the result of touch detection, the control logic changes the way to use data which decide start timings of display and no display. The start timings of display and non-display terms in a display frame period can be changed depending on the result of touch detection readily.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: June 11, 2019
    Assignee: Synaptics Japan GK
    Inventor: Takayuki Noto
  • Patent number: 10305709
    Abstract: A semiconductor device includes first and second buffers respectively outputting reception data and clock signals; a latch circuit latching the reception data signal in response to the reception clock signal; a delay circuitry delaying the reception clock signal by a set delay time; and a delay control circuitry which searches a first delay time while increasing the set delay time from an initial value; searches a second delay time while increasing the set delay time from the first delay time; searches a third delay time while decreasing the set delay time from the second delay time; and determines an optimum delay time from the first and third delay times. The first and third delay times are determined so that the reception data is stabilized to a first value and the second delay time is determined so that the reception data is stabilized to a second value.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: May 28, 2019
    Assignee: Synaptics Japan GK
    Inventors: Yoshihiko Hori, Takefumi Seno, Keiichi Itoigawa, Jun Kurosawa, Takashi Tamura, Hideaki Kuwada, Kazuhiko Kanda, Tomoo Minaki
  • Patent number: 10297189
    Abstract: A display driver for driving a display panel includes a delay circuit configured to receive first image data and output the received first image data with a delay; an image data processing circuit configured to select a selected image data processing operation from among a plurality of predefined image data processing operations in response to image format information specifying the format of the first image data, and generate second image data by performing the selected image data processing operation on the first image data received from the delay circuit; and a drive circuitry driving the display panel in response to the second image data. The amount of the delay is controlled in response to the image format information.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: May 21, 2019
    Assignee: Synaptics Japan GK
    Inventor: Hiroshi Morimoto
  • Patent number: 10270363
    Abstract: An inverter circuit includes: a first P-channel MISFET having a source connected to a positive-side terminal and a drain connected to an output terminal; a first N-channel MISFET having a source connected to a negative-side terminal and a drain connected to the output terminal; a first delay element connected between a gate of the first P-channel MISFET and an input terminal to which an input signal is supplied; first switch element connected in parallel with the first delay element between the input terminal and the gate of the first P-channel MISFET; a second delay element connected between the input terminal and a gate of the first N-channel MISFET; and a second switch element connected in parallel with the second delay circuit between the input terminal and the gate of the first N-channel MISFET. The first and second switch elements operate in response to a potential on the output terminal.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: April 23, 2019
    Assignee: Synaptics Japan GK
    Inventor: Naoji Shimizu
  • Patent number: 10250259
    Abstract: A system and method for digital signal reception comprise outputting first and second digital transmission signals complementary to each other. Further, a first and second output signals are outputted. The first output signal has a logical value based on a product of a logical value of the first digital transmission signal and a logical value complementary to a logical value of the second digital transmission signal is outputted. The second output signal has a logical value based on a sum of a logical value complementary to the logical value of the first digital transmission signal and the logical value of the second digital transmission signal.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: April 2, 2019
    Assignee: Synaptics Japan GK
    Inventor: Tsuyoshi Kuroiwa