Abstract: A halt period is inserted between a drive period in an odd-numbered field and a drive period in an even-numbered field in interlace driving. When drive signals driving subpixels are time-divisionally supplied to the display panel in units of subpixel types, switch control signals controlling source line switches which distribute the drive signals associated with respective subpixels to the corresponding source lines are generated so that the number of switching of the source line switches are reduced.

Abstract: Provided are a touch display control device and an information terminal device, which are arranged so that the noise resulting from the actions for activation and display on a display panel, and the noise caused by the actions of activation and detection on a touch sensor never affects each other, and are useful for suppressing the elicitation of the difference in brightness attributed to non-display in a display frame. The information terminal device includes: a display controller operable to change start timings of display and non-display periods in a cycle of a frame synchronizing signal of a display frame, in each cycle of the frame synchronizing signal or each sequence of cycles thereof; and a touch panel controller operable to perform the activation of a touch panel and a touch detection during the non-display period.

Abstract: An image processing apparatus includes: a first circuit which calculates values f(RPi), f(GPi) and f(BPi) by applying a function f(x) to an R grayscale value RPi, a G grayscale value GPi and a B grayscale value BPi of each pixel i of a first image; a second circuit which calculates values f(RQi), f(GQi) and f(BQi) by applying the function f(x) to an R grayscale value RQi, a G grayscale value GQi and a B grayscale value BQi of each pixel i of a second image; and a similarity calculation circuit which calculates a degree of similarity between the first and second images depending on |f(RPi)?f(RQi)|, |f(GPi)?|f(GQi)| and |f(BPi)?f(BQi)| associated with each pixel i of the first and second images. The function f(x) is a convex function monotonically non-decreasing in the domain of definition.

Abstract: A touch panel device includes a touch panel including sensing electrodes, a selector circuitry; a sensing circuitry configured to generate sensed signals having signal levels depending on self-capacitances of connected ones of the sensing electrodes, and a processor configured to perform touch sensing of the touch panel, based on the sensed signals. When the touch panel device is placed in a first state, the selector circuitry electrically connects first sensing electrodes to the sensing circuitry in each operation cycle. When the touch panel device is placed in a second state, the selector circuitry electrically connects second sensing electrodes to the sensing circuitry in each operation cycle. The number of the second sensing electrodes connected to the sensing circuitry in each operation cycle for the second state is less than the number of the first sensing electrodes connected to the sensing circuitry in each operation cycle for the first state.

Abstract: A driver includes a temperature sensor, a drive circuitry configured to drive a source line of a liquid crystal display panel, and a precharge circuitry configured to perform a precharge operation of the source line. When a measured temperature by the temperature sensor is in a first temperature range, the precharge circuitry selectively performs the precharge operation of the source line in response to the grayscale level indicated by the image data. When the measured temperature is in a second temperature range lower than the first temperature range, the precharge circuitry performs a selected one of first and second operations. The first operation includes unconditionally performing the precharge operation of the source line independently of the grayscale level indicated by the image data, and the second operation includes unconditionally omitting the precharge operation of the source line independently of the grayscale level indicated by the image data.

Abstract: A touch panel controller is provided with a calibration circuit that performs offset adjustment with respect to input signals of a plurality of detection circuits corresponding to a plurality of X electrodes of the touch panel, and a storage device that stores first parameter data that specifies an offset adjustment operation of the calibration circuit, and second parameter data for correction for the first parameter data.

Abstract: A display panel driver includes a scaler circuit performing image enlargement processing on input image data corresponding to an input image to generate ?-times enlarged image data corresponding to an ?-times enlarged image (? is a number larger than one which cannot be represented as 2k); and a driver section driving a display panel. In calculating a pixel value of a target pixel of the ?-times enlarged image, the scaler circuit generates enlarged image data including 2n-times enlarged image data corresponding to a 2n-times enlarged image obtained by enlarging the input image with an enlargement factor of 2n (n is the smallest integer determined so that 2n is larger than ?), and calculates the pixel value of the target pixel from the 2n-times enlarged image data through interpolation processing of pixel values of pixels of the 2n-times enlarged image corresponding to the target pixel of the ?-times enlarged image.

Abstract: A semiconductor device and a mobile terminal are described herein. In one example, a semiconductor device is provided that includes: a power-source part; an interface part; a logic part; and a driving part. In the semiconductor device, the power-source part includes a power-source-cutoff-detection circuit operable to detect a first state in which supply of an external power source is cut off. The logic part includes: a data-cutoff-detection circuit operable to detect a second state in which supply of stream data accompanied by synchronizing signals from outside the semiconductor device is cut off undesirably; and a control circuit operable to perform control for having the driving part cope with the power source cutoff with the power-source-cutoff-detection circuit detecting the first state or the data-cutoff-detection circuit detecting the second state.

Abstract: The overdrive amplifier may include: a differential input circuit arranged by connecting, in a folded-cascode style, input transistors supplied with an input signal at gates, and feedback input transistors accepting the feedback of an output signal at respective gates; a current mirror load having mirror input current paths connected to current paths of the feedback input transistors, and mirror output current paths connected to current paths of the input transistors; an output circuit accepting the input of output control signals from the mirror output current paths of the current mirror load; and an overdrive circuit which causes bias currents of directions which boost an output of the output circuit, depending on the output control signals, to pass through the current mirror load based on the output control signals in an overdrive period.

Abstract: a display driver is provided which drives a display panel. The display driver includes first and second buffer amplifiers associated with first and second pixels positioned adjacent in a horizontal direction; first and second connection switches; and a controller. Each of the first and second buffer amplifiers includes: a differential input circuit including a MOS transistor pair, first and second drain interconnections; an active load circuit connected to the first and second drain interconnections; and an output stage. The first connection switch is connected between the output nodes of the first and second buffer amplifiers. The second connection switch is connected between the first drain interconnections of the first and second buffer amplifiers. The controller controls the first and second switches in response to image data associated with the first and second pixels.

Abstract: The booster precharges a boost-voltage-output terminal to a predetermined voltage before voltage-boosting start by a charge-pump circuit in the booster. While alternately switching one capacitive electrode of a pumping capacitance between first and second voltages, the charge-pump circuit periodically applies a third voltage to the other capacitive electrode, in which the voltage is boosted by lifting up the third voltage each switching. The resultant boost voltage is successively supplied to a stabilization capacitance through a MOS switch circuit for output. Thus, a boost voltage boosted to a sum voltage of the second and third voltages can be obtained. Using a precharge voltage produced by the precharge circuit in the booster as the third voltage can make a MOS switch circuit operable to supply the third voltage and the MOS switch circuit for boost voltage output smaller than a voltage under the sum voltage of the second and third voltages.

Abstract: A semiconductor device includes a first structure component comprising a first transistor, a first dummy pattern, a second structure component comprising a second transistor and a second dummy pattern. The first structure component and the first dummy pattern have a first height, and the second structure component and the second dummy pattern have a second height lower than the first height.

Abstract: An image processing circuit includes: a representative-values calculation circuit and an all-combinations comparing compression circuit. The representative-values calculation circuit is configured to generate M datasets each including a plurality of representative values by performing a pre-process on image data associated with said N pixels, M being a natural number more than one and less than N. The all-combinations comparing compression circuit is configured to calculate correlations between two datasets selected from said M datasets for all possible combinations of the two datasets, to select a compression process from a plurality of compression processes in response to the calculated correlations, and to generate said compressed imaged data by compressing said M datasets by using said selected compression process. The image processing circuit may be incorporated in a display panel driver.

Abstract: The voltage transmission circuit includes: a multiplexer for transmitting positive and negative voltages ranging +VDD to ?VDD selectively; and a demultiplexer for receiving the positive and negative voltages and output them at positive and negative outputs. The voltage transmission circuit is arranged by use of elements each having a withstand voltage of which the absolute value is not 2|VDD|, but |VDD|. While transmitting positive voltages, the multiplexer is configured not to be applied by negative voltages, the multiplexer and demultiplexer are controlled by signals each having a potential of 0 V to +VDD, and the demultiplexer outputs the positive voltages at the positive output. While transmitting negative voltages, the multiplexer is configured not to be applied by positive voltages, the multiplexer and the demultiplexer are controlled by signals each having a potential of ?VDD to 0 V, and the demultiplexer outputs the negative voltages at the negative output.

Abstract: A receiver circuit includes a CLK_LP circuit, a CLK_HS circuit, a DATA_LP circuit, a DATA_HS circuit and a malfunction detection circuit. The CLK_LP circuit and the CLK_HS circuit are connected to the clock lane. The DATA_LP circuit and the DATA_HS circuit are connected to the data lane. The malfunction detection circuit is configured to assert an HS-mode return signal when a first mode signal indicating the communication mode of the clock lane is set to the LP mode at a moment when the second mode signal indicating the communication mode of the data lane is switched from the HS mode to the LP mode. The CLK_LP circuit sets the first mode signal to the HS mode in response to the assertion of the HS-mode return signal.

Abstract: A display driver for a display device including a sync extraction circuit configured to generate a vertical sync source signal in response to a vertical sync period start instruction indicating a start of a vertical sync period, a timing generator configured to generate an internal vertical sync signal in response to the vertical sync source signal; and a drive circuit configured to drive the display panel in synchronization with the internal vertical sync signal.

Abstract: A buffer memory and display drive device are described herein. In one example, a buffer memory is arranged so that write and read address counters are controlled according to a wraparound method, and subjected to no reset in count value, which enables the avoidance of data destruction in a boundary portion of a block. In the buffer memory, block head addresses of the write and read address counters are managed centrally. So, even in the event of undesired change in count value, the influence thereof can be intercepted halfway. While reducing the memory capacity of the buffer memory which is supplied with data in blocks, the following are made possible: to prevent the deviation in read data owing to an undesired change in the address counter from lasting; and to prevent data, handled in blocks, from disappearing near a block boundary.

Abstract: A cell library readable by a computer device includes cell data of a power supply reinforcement cell, specifying a conductive path that connects high-potential power supply routings located on both sides of one low-potential power supply routing with the routing interposed therebetween or low-potential power supply routings located on both sides of one high-potential power supply routing with the routing interposed therebetween, in data of plural cells which is used in designs of a semiconductor device including plural high-potential power supply routings, connected to a high-potential power supply trunk, which are separated from each other and are placed in parallel with each other, plural low-potential power supply routings, connected to a low-potential power supply trunk, which are placed alternately and in parallel with the high-potential power supply routings, and functional circuits which are formed in regions located between the high-potential power supply routings and the low-potential power supply ro

Abstract: A large scale integrated circuit chip includes a semiconductor circuit having a multilayered wiring structure, a metal guard ring surrounding the semiconductor circuit, and a plurality of external connection terminals, on a semiconductor circuit. The plurality of external connection terminals connect to an uppermost-layer wiring of the multilayered wiring structure and are exposed on a surface of the large scale integrated circuit chip. A predetermined external connection terminal conducts to a predetermined wiring through a conductive via within the guard ring and conducts to a conductive piece through another conductive via outside the guard ring. One side of the external connection terminal extending over the guard ring connects to the conductive piece, and the other side of the external connection terminal connects to the uppermost-layer wiring within the guard ring. Thus, a cutout part is not necessary in the guard ring.

Abstract: An integrated circuit device boosts an output voltage which is to be boosted based on the reference power supply voltage, based on another power supply voltage before the reference power supply voltage is supplied.