Abstract: In a described example, a circuit includes a first bipolar junction transistor (BJT) having a first base, a first emitter and a first collector. A second BJT has a second base, a second emitter and a second collector, in which the first collector is coupled to the second collector. A bandgap core circuit has first and second core inputs and a bandgap output. The first core input is coupled to the first emitter, the second core input is coupled to the second emitter, and the first and second bases are coupled to the bandgap output.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to generate a modulation protocol to output audio. An example apparatus includes a modulation circuit including a first input, a second input, a first output, and a second output; a first gate coupled to the first output of the modulation circuit; a second gate coupled to the second output of the modulation circuit; a first multiplexer including a first input coupled to the first output of the modulation circuit, a second input coupled to the output of the second gate, and an output coupled to a first switch; and a second multiplexer including a first input coupled to the second output of the modulation circuit, a second input coupled to the output of the first gate, and an output coupled to a second switch.

Abstract: An integrated circuit includes: a processor; a receiver coupled to the processor; and memory coupled to the processor. The memory stores resource coordinator instructions that, when executed by the processor, cause the processor to: maintain a plurality of active secure sessions; identify a priority session trigger; and allocate receiver resources for incoming packets related to the plurality of active secure sessions based on the priority session trigger.

Abstract: An example apparatus includes: a switch having a first current terminal, a second current terminal and a control terminal, the first current terminal adapted to be coupled to a first capacitor, the second current terminal adapted to be coupled to a second capacitor; a comparator having a comparator input and a comparator output, the comparator input coupled to a configuration terminal; a deglitch circuit having a deglitch input and a deglitch output, the deglitch input coupled to the comparator output, the deglitch circuit having a deglitch duration between a first duration and a second duration; and a universal serial bus (USB) controller having a controller output and a controller input, the controller output coupled to the control terminal, the controller input coupled to the deglitch output.

Abstract: A short circuit detection circuit includes a current terminal, a sense resistor, an amplifier, and a resistor-capacitor ladder. The sense resistor is coupled to the current terminal, and is configured to develop a sense voltage proportional to a current through the current terminal. The amplifier is coupled to the sense resistor, and is configured to generate a scaled current proportional to the sense voltage. The resistor-capacitor ladder is coupled to the amplifier, and is configured to generate a measurement voltage that represents a surface temperature rise due to the current through the current terminal.

Abstract: A method for adaptive loop filtering of a reconstructed picture in a video encoder is provided that includes determining whether or not sample adaptive offset (SAO) filtering is applied to the reconstructed picture, and using adaptive loop filtering with no offset for the reconstructed picture when the SAO filtering is determined to be applied to the reconstructed picture.

Abstract: Deblocking filtering is provided in which an 8×8 filtering block covering eight sample vertical and horizontal boundary segments is divided into filtering sub-blocks that can be independently processed. To process the vertical boundary segment, the filtering block is divided into top and bottom 8×4 filtering sub-blocks, each covering a respective top and bottom half of the vertical boundary segment. To process the horizontal boundary segment, the filtering block is divided into left and right 4×8 filtering sub-blocks, each covering a respective left and right half of the horizontal boundary segment. The computation of the deviation d for a boundary segment in a filtering sub-block is performed using only samples from rows or columns in the filtering sub-block. Consequently, the filter on/off decisions and the weak/strong filtering decisions of the deblocking filtering are performed using samples contained within individual filtering blocks, thus allowing full parallel processing of the filtering blocks.

Abstract: A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.

Abstract: Described embodiments include a circuit for voltage regulator startup. The circuit includes a voltage regulation circuit having first and second regulator inputs and a regulator output. A startup circuit has a startup input coupled to the first regulator input, and a startup output. A reference generation circuit has first and second reference inputs and first and second reference outputs. The first reference input is coupled to the regulator output. The second reference input is coupled to the startup output, and the first reference output is coupled to a reference output terminal and to the second regulator input. A reference detection circuit has a first detection input coupled to the regulator output, and a second detection input coupled to the second reference output, and provides a reference ready signal responsive to a reference voltage being within a reference specification.

Abstract: A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, a noise measurement circuit configured to measure electrical noise on the node, and the controller receiving the measurement of noise from the noise measurement circuit.

Abstract: A circuit configured to: generate a reference clock signal; generate an excitation signal at a target frequency having a period that is a first integer number of cycles of the reference clock signal; update a driver circuit at an update frequency having a period that is a second integer number of cycles of the reference clock signal; digitize sense signals resulting from the excitation signal at a frequency having a period that is a third integer number of cycles of the reference clock signal; identify a fourth integer number of sense signal samples; optionally utilize an excitation control signal having a period that is a fifth integer number of cycles of the reference clock signal; and minimize harmonics at the target frequency of the excitation signal based on the first integer number, the second integer number, the third integer number, the fourth integer number, and possibly the fifth integer number.

Abstract: An inductive current digital-to-analog converter (DAC) includes: a power supply input adapted to be coupled to a power supply; a load terminal adapted to be coupled to a load; an inductor between the power supply input and the load terminal; and inductor current control circuitry. The inductor current control circuitry has: a sense signal input configured to receive a sense signal representative of the inductor current; a control code input configured to receive a control code; a set of switches having respective control terminals; and a set of control circuit outputs coupled to the respective control terminals of the set of switches. The inductor current control circuitry is configured to adjust control signals provided to the set of control circuit outputs based on the sense signal and the control code.

Abstract: In described examples, a coherent memory system includes a central processing unit (CPU) and first and second level caches. The memory system can include a pipeline for accessing data stored in one of the caches. Requestors can access the data stored in one of the caches by sending requests at a same time that can be arbitrated by the pipeline.

Abstract: A system comprises a digital processing circuit, a frequency modulator, an amplitude modulator, and an adder. The digital processing circuit receives an input signal and a correlation signal and generates a frequency tuning parameter and an amplitude modulation parameter. The frequency modulator generates a frequency modulation signal and the correlation signal. The amplitude modulator receives the amplitude modulation parameter and generates an amplitude modulation signal. The adder receives the frequency tuning parameter and the frequency modulation signal and generates a control signal. In some implementations, the system further comprises a DC feedback circuit that receives the input signal and generates a DC compensation signal. In some implementations, the system further comprises a temperature sensor, a temperature compensation circuit, and a second adder.

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

Abstract: A control circuit for an inverter. The control circuit includes a first pulse width modulation (PWM) module configured to produce first and second complementary PWM signals, and a second PWM module configured to produce a third and fourth complementary PWM signals. PWM switching logic is coupled to the first and second PWM modules and is adapted to be coupled to a switch network. The switch network includes first, second, third, and fourth switches coupled in series between a first voltage terminal and a second voltage terminal. The PWM switching logic is configured to produce control signals for each of the first, second, third, and fourth switches in response to the first and second complementary PWM signals and to the third and fourth complementary PWM signals.

Abstract: In described examples, a processor system includes a processor core that generates memory write requests, and a cache memory with a memory controller having a memory pipeline. The cache memory has cache lines of length L. The cache memory has a minimum write length that is less than a cache line length of the cache memory. The memory pipeline determines whether the data payload includes a first chunk and ECC syndrome that correspond to a partial write and are writable by a first cache write operation, and a second chunk and ECC syndrome that correspond to a full write operation that can be performed separately from the first cache write operation. The memory pipeline performs an RMW operation to store the first chunk and ECC syndrome in the cache memory, and performs the full write operation to store the second chunk and ECC syndrome in the cache memory.

Abstract: A method for communicating over a wireless backhaul channel comprising generating a radio frame comprising a plurality of time slots, wherein each time slot comprises a plurality of symbols in time and a plurality of sub-carriers in a system bandwidth, broadcasting a broadcast channel signal comprising a transmission schedule to a plurality of remote units in a number of consecutive sub-carriers centered about a direct current (DC) sub-carrier in at least one of the time slots in the radio frame regardless of the system bandwidth, and transmitting a downlink (DL) control channel signal and a DL data channel signal to a first of the remote units, wherein the DL data channel signal is transmitted by employing a single carrier block transmission scheme comprising a Discrete Fourier Transform (DFT) spreading for frequency diversity.

Abstract: In described examples, ownership of a network protocol-based session is distributed across multiple entities. A session is established between a remote entity and a first processing node on a local device, such that the first processing node is the session owner of the session on the local device. During the session, ownership of the session is transferred from the first processing node to a second processing node on the local device, such that the second processing node becomes the session owner of the session on the local device. The session is then operated between the remote entity and the second processing node as the session owner.

Abstract: A method and user equipment for channel state information (CSI) reporting are described. The method receives a channel quality indicator request. The method determines a channel quality indicator based on a CSI reference resource. The method transmits a CSI report that includes the channel quality indicator via a Physical Uplink Control CHannel (PUCCH) on an uplink subframe. The CSI reference resource belongs to a subframe subset for which the CSI report is sent. The CSI reference resource includes overhead of Demodulation Reference Signals according to a corresponding rank report.