Abstract: An oscillator circuit includes a bulk acoustic wave resonator, a differential active inductor circuit, and a gain circuit. The differential active inductor circuit is configured to bias the bulk acoustic wave resonator. The differential active inductor circuit is coupled between the bulk acoustic wave resonator and a power supply terminal. The gain circuit is coupled to the bulk acoustic wave resonator.

Abstract: In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror and an amplifier, where the amplifier is coupled to a pin of the chip. The oscillator circuit also includes a first switch coupled to the pin, a second switch coupled to the pin and to a charging resistor, and a third switch coupled to the amplifier and an internal resistor, where the internal resistor is internal to the chip. The oscillator circuit includes a bias current source coupled to the current mirror. The system includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system also includes an external capacitor coupled to the pin and coupled in parallel to the external resistor, where the external capacitor is external to the chip.

Abstract: A method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. The openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second LOCOS structures having a first thickness. A polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. A blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second LOCOS structure while leaving the first LOCOS structure protected by the polysilicon layer. The silicon substrate under the second LOCOS structure is further oxidized such that the second LOCOS structure has a second thickness greater than the first thickness.

Abstract: In at least one example, an apparatus includes a logic circuit having a switch control output and first and second logic circuit inputs. A pulse generator has a generator output coupled to the first logic circuit input. An elevated temperature detector has a detector output and a temperature sensor. The detector output is coupled between the second logic circuit input and the temperature sensor.

Abstract: Systems and methods for developing a novel public/private key pair having unique properties are disclosed, whereby standard data security operations in existing data security infrastructures return a data integrity validation result—but do not provide the intended data security of such infrastructures. These novel keys are referred to as degenerate keys and may be used to replace the public and private keys in existing public/private key cryptosystems. Because degenerate key data integrity validation may leverage existing data security infrastructures that are already widely-implemented, such examples may be applied immediately and configured to seamlessly transition from integrity only modes back to secure modes. In some instances, the degenerate key examples described herein may be employed during a software testing and/or factory validation stage of product development to allow for data integrity validation before burning in a developer's active (i.e.

Abstract: An integrated circuit includes a shallow P-type well (SPW) below a surface of a semiconductor substrate and a shallow N-type well (SNW) below the surface. The SPW forms an anode of a diode and the SNW forms a cathode of the diode. The SNW is spaced apart from the SPW by a well space region; and a thin field relief oxide structure lies over the well space region.

Abstract: A method and apparatus for a low complexity transform unit partitioning structure for High Efficiency Video Coding (HEVC). The method includes determining prediction unit size of a coding unit, and setting the size of transform unit size of Y, U and V according to the prediction unit size of the coding unit.

Abstract: A method for adaptive loop filtering is provided that includes determining a coefficient value for each coefficient position of an adaptive loop filter, applying the adaptive loop filter to at least a portion of a reconstructed picture using the coefficient values, and entropy encoding coefficient values into a compressed bit stream using predetermined short binary codes, wherein the short binary code used depends on the coefficient position of the coefficient value.

Abstract: A method for manufacturing a package includes positioning a copper layer above a die. A zinc layer is positioned on the copper layer. The zinc and copper layers are then heated to produce a brass layer, the brass layer abutting the copper layer. Further, a polymer layer is positioned abutting the brass layer.

Abstract: Techniques for signaling of sample adaptive offset (SAO) information that may reduce the coding rate for signaling such information in the compressed bit stream are provided. More specifically, techniques are provided that allow SAO information common to two or more of the color components to be signaled using one or more syntax elements (flags or indicators) representative of the common information. These techniques reduce the need to signal SAO information separately for each color component.

Abstract: A method for derivation of a temporal motion data (TMD) candidate for a prediction unit (PU) in video encoding or video decoding is provided. The derived TMD candidate is for inclusion in an inter-prediction candidate list for the PU. The method includes determining a primary TMD position relative to a co-located PU in a co-located largest coding unit (LCU), wherein the co-located PU is a block in a reference picture having a same size, shape, and coordinates as the PU, and selecting at least some motion data of a secondary TMD position as the TMD candidate when the primary TMD position is in a bottom neighboring LCU or in a bottom right neighboring LCU of the co-located LCU, wherein the secondary TMD position is determined relative to the co-located PU.

Abstract: A communication device in a network may receive a stream of frames from the network, in which each frame includes one or more beacon packets. A communication protocol being used by the network may be identified by tracking a preselected field within a sequence of beacon packets, in which the preselected field varies in a first known manner for a first protocol and in a second known manner for a second protocol. The communication device may then join to the network using the identified communication protocol to transmit and receive data.

Abstract: An electronic device has a first circuit, a second circuit, and an isolation circuit, the isolation circuit having an input and an output, the first circuit including a signal generator having an output, the output of the signal generator coupled to the input of the isolation circuit. The second circuit includes a rectifier circuit and a signal detector circuit, the rectifier circuit having a rectifier input coupled to the output of the isolation circuit, and the signal detector circuit having an input coupled to the output of the isolation circuit.

Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.

Abstract: In described examples, a method comprises forming a patterned region on a first surface of the semiconductor substrate. The method also comprises forming circuitry in the patterned region. The method further comprises forming a metallic layer on a second surface of the semiconductor substrate, in which the second surface opposes the first surface; and forming a carbon layer on the metallic layer.

Abstract: In a described example, an electrical apparatus includes a substrate having a first surface and lead pads on the first surface of the substrate for surface mounting components. A ribbon wire bond is provided having open ends and a central portion between the open ends, the open ends of the ribbon wire bond connected to the lead pads. An electrical component is bonded to the central portion of the ribbon wire bond. The central portion of the ribbon wire bond and the electrical component are spaced from the first surface of the substrate.

Abstract: A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.

Abstract: A digital micromirror device comprises an array of micromirror pixels, the array comprising a first micromirror pixel and a second micromirror pixel. The first micromirror pixel comprises a hinge, where the hinge is configured to tilt toward a first raised address electrode and toward a second raised address electrode. The first micromirror pixel also comprises a first micromirror coupled to the hinge, where the first micromirror has a sculpted edge. The second micromirror pixel comprises a second micromirror, where a first gap between a first point on the sculpted edge and a nearest point to the first point on the second micromirror is larger than a second gap between a second point on the sculpted edge and a nearest point to the second point on the second micromirror.

Abstract: Techniques related to a technique comprising dividing an update into a number of portions, generating, for the first portion, a first portion hash value, generating, for the second portion, a second portion hash value, generating a first branch hash value comprising a hash of a concatenation of the first portion hash value and the second portion hash value, generating a root hash value by concatenating the first branch hash value and a second branch hash value, generating a signature based on the root hash value and a private key, generating an update header comprising the signature, the root hash value, and a hash tree comprising first and second portion hash values, the first branch hash value, and the root hash value, transmitting the update header to a client device for authentication, and transmitting one or more of the number of portions to the client device.

Abstract: In one disclosed embodiment, a processor includes a first execution unit and a second execution unit, a register file, and a data path including a plurality of lanes. The data path and the register file are arranged so that writing to the register file by the first execution unit and by the second execution unit is allowed over the data path, reading from the register file by the first execution unit is allowed over the data path, and reading from the register file by the second execution unit is not allowed over the data path. The processor also includes a power control circuit configured to, when a transfer of data between the register file and either of the first and second execution units uses less than all of the lanes, power down the lanes of the data path not used for the transfer of the data.