Abstract: Disclosed embodiments relate to a streaming engine employed in, for example, a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.

Abstract: In some examples, a controller circuit comprises: a voltage subtractor circuit having a subtractor output and first and second subtractor inputs, in which the first subtractor input is adapted to be coupled to a first current terminal of a transistor, the second subtractor input is adapted to be coupled to a second current terminal of the transistor; a gate control circuit having a gate control input and a gate control output, the gate control input coupled to the subtractor output, the gate control output adapted to be coupled to a gate of the transistor; and a discharge circuit having a discharge circuit input and a discharge circuit output, the discharge circuit input coupled to the gate control circuit, the discharge circuit output adapted to be coupled to the first current terminal of the transistor.

Abstract: A battery charger includes a battery power regulator configured to set a charge signal provided to a battery based on a charge control signal and charge enable signal. The battery charger also includes a controller configured to provide the charge control signal to the battery power regulator. The controller is also configured to temporarily de-assert the charge enable signal for a predetermined amount of time in response to determining that a change is needed in the charge control signal. The controller is further configured to re-assert the charge enable signal after the predetermined amount of time.

Abstract: Described embodiments include a circuit for limiting power converter output ripple. A first transistor has a first current terminal receiving an input voltage, and a second current terminal coupled to a first capacitor. A second transistor has a third current terminal coupled to the first capacitor, and a fourth current terminal is coupled to a second capacitor. A third transistor has a fifth current terminal coupled to the second capacitor, and a sixth terminal coupled to a filter input. A fourth transistor has a seventh current terminal coupled to the second current terminal, and an eighth current terminal coupled to the sixth current terminal. A fifth transistor has a ninth current terminal coupled to the fourth current terminal, and a tenth current terminal coupled to the sixth current terminal.

Abstract: A method of BLE-Mesh communications includes providing a dual-mode BLE-Mesh device including dual-mode RF driver, dual-mode manager, a BLE stack for BLE operations. and a mesh stack for mesh operations in a BLE-mesh network having a BLE relay device and a functional end BLE device. The BLE-mesh device has a periodic set of time indexed data slots common throughout the BLE-mesh network which provides a BLE event timeline for BLE connection events. The dual-mode BLE device implements an event clustering algorithm that delays or advances mesh events with respect to a timing the BLE connection events for clustering together their respective occurrences into continuous BLE/Mesh events to reduce a duty cycle by reducing a number of transitions from active mode to sleep mode and from sleep mode to active mode. The BLE-Mesh device communicates in the BLE-mesh network using the continuous BLE/Mesh events with at least one mesh device.

Abstract: An adaptive clamp circuit includes a clamp circuit and a clamp control circuit. The clamp circuit includes a first transistor, a second transistor, and a variable resistor. The first transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal is coupled to a switching terminal. The second current terminal is coupled to a ground terminal. The second transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal of the second transistor is coupled to the control terminal of the first transistor. The second current terminal of the second transistor is coupled to the switching terminal. The variable resistor is coupled between the control terminal of the second transistor and the ground terminal. The clamp control circuit is coupled between the switching terminal and the variable resistor.

Abstract: An electronic circuit includes: a memory including a data input, an address input, a command input, and a data output; a register having a data input coupled to the data output of the memory; a comparator circuit having a first data input coupled to the data output of the memory, and a second data input coupled to a data output of the register; an inverter circuit having a data input coupled to the data output of the register, and a data output coupled to the data input of the memory; and a controller having a command output coupled to the command input of the memory, an address output coupled to the address input of the memory, and a fault input coupled to a data output of the comparator circuit, where the controller is configured to determine whether the memory has a fault based on the fault input of the controller.

Abstract: A network includes at least one node to communicate with at least one other node via a wireless network protocol. The node includes a network configuration module to periodically switch a current node function of the node between an intermediate node function and a leaf node function. The switch of the current node function enables automatic reconfiguration of the wireless network based on detected communications between the at least one node and at least one intermediate node or at least one leaf node via the wireless network protocol.

Abstract: A fully-differential amplifier (FDA) includes a core differential amplifier and a common-mode input voltage control circuit. The core differential amplifier includes differential inputs. The common-mode input voltage control circuit is coupled to the differential inputs. The common-mode input voltage control circuit is configured to generate an error signal as a difference of an input common mode voltage at the differential inputs and a target common mode input voltage (VICM); and to adjust the input common mode voltage to the VICM based on the error signal.

Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.

Abstract: An electronic device includes a substrate having a surface, functional metallic traces on a first portion of the surface that are electrically connected to carry current in the electronic device and have a first density, and dummy metallic traces on a second portion of the surface that are electrically isolated from the functional metallic traces and have a second density that is within at least 50% of the first density.

Abstract: In accordance with described examples, a method determines if a velocity of an object detected by a radar is greater than a maximum velocity by receiving on a plurality of receivers at least one frame of chirps transmitted by at least two transmitters and reflected off of the object. A velocity induced phase shift (?d) in a virtual array vector S of signals received by each receiver corresponding to a sequence of chirps (frame) transmitted by each transmitter is estimated. Phases of each element of virtual array vector S are corrected using ?d to generate a corrected virtual array vector Sc. A first Fourier transform is performed on the corrected virtual array vector Sc to generate a corrected virtual array spectrum to detect a signature that indicates that the object has an absolute velocity greater than a maximum velocity.

Abstract: A data storage circuit includes memory, an error correcting code (ECC) storage circuit, and control circuitry. The memory is configured to store a data value comprising a plurality of fields. Each of the fields is independently writable. The ECC storage circuit is configured to store an ECC value corresponding to the data value. The control circuitry is configured to receive a field value to be written into one of the fields, and store the field value in the one of the fields by writing only the field value to the memory. The control circuitry is also configured to retrieve the ECC value from the ECC storage circuit, compute an updated ECC value based on the ECC value retrieved from the ECC storage circuit and the field value, and store the updated ECC value in the ECC storage circuit.

Abstract: The vector data path is divided into smaller vector lanes. A register such as a memory mapped control register stores a vector lane number (VLX) indicating the number of vector lanes to be powered. A decoder converts this VLX into a vector lane control word, each bit controlling the ON of OFF state of the corresponding vector lane. This number of contiguous least significant vector lanes are powered. In the preferred embodiment the stored data VLX indicates that 2VLX contiguous least significant vector lanes are to be powered. Thus the number of vector lanes powered is limited to an integral power of 2. This manner of coding produces a very compact controlling bit field while obtaining substantially all the power saving advantage of individually controlling the power of all vector lanes.

Abstract: A circuit includes a digital-to-analog converter (DAC) and a compensation circuit. The DAC has first and second terminals. The compensation circuit includes a capacitor and a transistor. The capacitor has first and second terminals, with the first terminal of the capacitor coupled to the first terminal of the DAC. The transistor has a source coupled to the second terminal of the capacitor, and has a gate coupled to the second terminal of the DAC.

Abstract: A digital system includes a non-volatile calculating register having a set of latches configured to perform a calculation. A set of non-volatile storage cells is coupled to the set of latches. Access detection logic is coupled to the calculating register and is operable to initiate a calculation of a next value by the calculating register each time the calculating register is accessed by an accessing module. The access detection logic is operable to cause the next value to be stored in the set of non-volatile storage cells at the completion of the calculation as an atomic transaction. After a power loss or other restore event, the contents of the calculating register may be restored from the non-volatile storage cells.

Abstract: A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

Abstract: In one example, a method comprises filling a tube made of a same material with a dipolar gas; sealing a portion of the tube to form a container enclosing the dipolar gas. The method further comprises forming an electromagnetic reflective coating inside or outside the container, the electromagnetic reflective coating having an opening; and positioning an antenna at the opening.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream recalled memory. Streams are started by one of two types of stream start instructions. A stream start ordinary instruction specifies a register storing a stream start address and a register of storing a stream definition template which specifies stream parameters. A stream start short-cut instruction specifies a register storing a stream start address and an implied stream definition template. A functional unit is responsive to a stream operand instruction to receive at least one operand from a stream head register. The stream template supports plural nested loops with short-cut start instructions limited to a single loop. The stream template supports data element promotion to larger data element size with sign extension or zero extension. A set of allowed stream short-cut start instructions includes various data sizes and promotion factors.

Abstract: IC apparatus, and manufacturing methods therefor, that include a power transistor and a thermoelectric device. The power transistor is constructed in a plurality of layers formed over a semiconductor substrate. The thermoelectric device is formed in one or more of the plurality of layers and is sensitive to temperature differences within the IC apparatus resulting from operation of the power transistor.