Abstract: A packaged integrated circuit (IC), comprising: a lead frame; one or more semiconductor dies on the lead frame, the one or more semiconductor dies including a first circuit and a second circuit; and a molding compound encapsulating the lead frame and the semiconductor die, the molding compound including a first cavity over the first circuit and a second cavity over the second circuit, in which at least one of the first or second cavities includes a second material different from the molding compound.

Abstract: A method for geometrically correcting a distorted input frame and generating an undistorted output frame includes capturing and storing an input frame in an external memory, allocating an output frame with an output frame size and dividing the output frame into output blocks, computing a size of the input blocks in the input image corresponding to each output blocks, checking if the size of the input blocks is less than the size of the internal memory and if not dividing until the required input block size of divided sub blocks is less than the size of the internal memory, programming an apparatus with input parameters, fetching the input blocks into an internal memory, processing each of the divided sub blocks sequentially and processing the next output block in step until all the output blocks are processed; and composing the output frame for each of the blocks in the output frame.

Abstract: A method for evaluating tests for fabricated integrated circuit (IC) chips includes providing, design for fault injection (DfFI) instances of an IC design that characterize activatable states of controllable elements in an IC chip based on the IC design. The method also includes fault simulating the IC design a corresponding identified test suite to determine a signature for faults and simulating the IC design with the DfFI instances activated to determine a signature for the DfFI instances. The method includes generating a DfFI-fault equivalence dictionary based on a comparison of the signature of the faults and DfFI instances and generating tests for a fabricated IC chip based on the IC design. The method includes receiving test result data characterizing the tests being applied against the fabricated IC chip with the DfFI instances activated and analyzing the test result data to determine an ability of the tests to detect the faults.

Abstract: A method comprises: forming a first metallization layer on a semiconductor die, the first metallization layer including a metal fuse; and forming a second metallization layer on the first metallization layer, in which the second metallization layer includes a thermal conductor spaced from the metal fuse, and the first metallization layer is between the second metallization layer and the semiconductor die.

Abstract: Multiple transform sizes improve video coding efficiency, but also increase the implementation complexity. Furthermore, both forward and inverse transforms need to be supported in various consumer devices. Embodiments provide a unified forward and inverse transform architecture that supports computation of both forward and inverse transforms for multiple transforms sizes using shared hardware circuits. The unified architecture exploits the symmetry properties of forward and inverse transform matrices to achieve hardware sharing across different the transform sizes and also between forward and inverse transform computations.

Abstract: An apparatus includes an inverse radar sensor model processor and a grid mapping processor. The inverse radar sensor model processor receives radar sensor data for a time k from a radar sensor, generates object data based on the radar sensor data, and calculates instantaneous masses at the time k for each cell in a field of view (FOV) of the radar sensor based on the object data and a sensor characteristic. The inverse radar sensor model processor outputs the calculated instantaneous masses to the grid mapping processor, which also receives accumulated masses for each cell in the FOV for a time period 0:k?1. An accumulated mass represents a combination of instantaneous masses for the cell at each time increment in the time period 0:k?1. The grid mapping processor generates updated accumulated masses for a time period 0:k.

Abstract: One example includes an ultrasonic ranging system. The system includes an ultrasonic transducer configured to transmit an ultrasonic signal and to receive reflected ultrasonic signal paths having been reflected from a plurality of target objects during a ranging operation. The system also includes a ranging processor configured to detect a location associated with the plurality of target objects based on monitoring phase information associated with the reflected ultrasonic signal paths.

Abstract: An apparatus comprises a transistor pair including a first metal oxide semiconductor field effect transistor (MOSFET) coupled to a second MOSFET. The first MOSFET includes a first gate terminal and a first drain terminal. The second MOSFET comprises a second gate terminal and a second drain terminal. The first gate terminal is configured to receive a first signal. The second gate terminal is configured to receive a second signal that is phase shifted with respect to the first signal. An output node is coupled to the first drain terminal and the second drain terminal and configured to output a third signal that is proportional to a power of the first signal and the second signal.

Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a particular duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.

Abstract: Techniques for executing machine learning (ML) models including receiving an indication to run an ML model on a processing core; receiving a static memory allocation for running the ML model on the processing core; determining that a layer of the ML model uses more memory than the static memory allocated; transmitting, to a shared memory, a memory request for blocks of the shared memory; receiving an allocation of the requested blocks; running the layer of the ML model using the static memory and the range of memory addresses; and outputting results of running the layer of the ML model.

Abstract: An integrated circuit has a substrate that includes a semiconductor material, and an interconnect region disposed on the substrate. The integrated circuit includes a thermal routing trench in the substrate. The thermal routing trench includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal routing trench has a thermal conductivity higher than the semiconductor material contacting the thermal routing trench. The cohered nanoparticle film is formed by an additive process.

Abstract: A method for dithering radar frames includes determining at least one of a chirp period Tc for radar chirps in a radar frame and a chirp slope S for radar chirps in the radar frame. In response to determining the chirp period Tc, a maximum chirp dither ?c(max) is determined, and for the radar frame N, a random chirp dither ?c(N) between negative ?c(max) and positive ?c(max) is determined. In response to determining the chirp slope S, a maximum slope dither ?(max) is determined, and for the radar frame N, a random slope dither ?(N) between negative ?(max) and positive ?(max) is determined. A radar sensor circuit generates radar chirps in the radar frame N based on the at least one of (1) the chirp period Tc and the random chirp dither ?c(N) and (2) the chirp slope S and the random slope dither ?(N).

Abstract: Several methods and systems for encoding of multimedia pictures are disclosed. In an embodiment, an occupancy level of a coded picture buffer (CPB) associated with a hypothetical reference decoder (HRD) is estimated at an instant of removal of an access unit corresponding to a multimedia picture from the CPB for decoding the access unit. A number of bits for encoding the multimedia picture is allocated based on the estimated occupancy level of the CPB. The multimedia picture is encoded based on the allocated number of bits.

Abstract: A method for encoding a multi-view frame in a video encoder is provided that includes computing a depth quality sensitivity measure for a multi-view coding block in the multi-view frame, computing a depth-based perceptual quantization scale for a 2D coding block of the multi-view coding block, wherein the depth-based perceptual quantization scale is based on the depth quality sensitive measure and a base quantization scale for the 2D frame including the 2D coding block, and encoding the 2D coding block using the depth-based perceptual quantization scale.

Abstract: Described embodiments include a test system having first, second and third circuits having the same design and configured to receive a same input signal. A majority voter circuit has a first voter input coupled to a first circuit output, a second voter input coupled to a second circuit output, a third voter input coupled to a third circuit output, and a voter output. The output signal is equal to a signal present at least two of the voter inputs. A discrepancy detector circuit has first, second and third discrepancy inputs coupled to the first, second and third circuit outputs, respectively. A discrepancy output is configured to: provide a first logic signal responsive to the first, second and third circuit outputs having equal values; and provide a second logic signal responsive to the first, second and third circuit outputs having unequal values.

Abstract: In a described example, a circuit includes a synchronization control circuit having a sync input and a sync control output, in which the sync input is coupled to a sync terminal configured to receive an external clock signal. An internal clock generator circuit has a control input and an output. The control input is coupled to the sync control output. An output circuit has first and second signal inputs, a mode control input and a clock output. The first signal input is coupled to the sync input, and the second signal input of the output circuit is coupled to the output of the internal clock generator circuit. The mode control input is coupled to the sync control output, and the clock output adapted to be coupled to a controller.

Abstract: In a described example, a device includes: a semiconductor substrate; a memory array on the semiconductor substrate, the memory array comprising rows and columns of memory cells in a Manhattan pattern, the memory cells having a pitch in a direction along the columns; and an array of micromirrors in a diamond pattern over the memory cells, the micromirrors coupled to corresponding memory cells, the micromirrors having a diagonal pitch length in the direction along the columns that is between 1.8 times the pitch and 2.2 times the pitch.

Abstract: One example described herein includes a power switch control system. The system includes a first monitoring terminal coupled to a first terminal of a power transistor and a second monitoring terminal coupled to a second terminal of the power transistor. The power transistor and the power switch control system can form an ideal diode between the first monitoring terminal arranged as an anode and the second monitoring terminal arranged as a cathode. The system further includes a reverse current controller coupled to the first monitoring terminal and the second monitoring terminal and is configured to control activation of the power transistor to conduct a reverse current from the second monitoring terminal to the first monitoring terminal in response to a reverse voltage arranged as a cathode voltage at the second monitoring terminal being greater than an anode voltage at the first monitoring terminal.

Abstract: A device includes a first transistor (M1) having a control terminal that is a first comparator input, a first terminal that can be coupled to a voltage source, and a second terminal that provides a first comparator output; a second transistor (M2) having a control terminal that is a second comparator input, a first terminal that can be coupled to the voltage source, and a second terminal that provides a second comparator output; a third transistor (M3) having a control terminal coupled to M1, and a first terminal coupled to ground; a fourth transistor (M4) having a control terminal coupled to M2, and a first terminal coupled to ground; first switches that couple M3 second terminal to M3 control terminal, and M4 second terminal to M4 control terminal; and second switches that couple M3 second terminal to the M2 second terminal, and M4 second terminal to the M1 second terminal.

Abstract: A network device serving two or more networks using periodic times slots for transmission events is configured to determine that one of the periodic time slots on one of the networks has or soon will collide with one of the periodic time slots on the other network by processing time stamps for events on each network. Either of the periodic time slots may be occasionally shifted by a time shift amount to avoid a collision between the periodic time slots on each network. Shifting the periodic time slots may be performed by transmitting a Bluetooth connection parameter update packet.