Abstract: An adjustable delay line includes a series of delay elements for adjusting the accumulative delay. Each element has a plurality of registers indicating to various devices within the delay element to be ‘on’ or ‘off’, thereby changing the time delay through the element. A master control indicates to the delay line whether to go faster (increment) or go slower (decrement). When one of these control signals is applied to the delay line, it is applied to half the elements, either the odd or the even numbered elements. Only one element will have its state changed by the increment or decrement control signal, and it will be the element for which the previous delay's corresponding element is already set or un-set depending upon the applicable case.

Abstract: An adjustable delay line includes a series of delay elements for adjusting the accumulative delay. Each element has a plurality of registers indicating to various devices within the delay element to be ‘on’ or ‘off’, thereby changing the time delay through the element. A master control indicates to the delay line whether to go faster (increment) or go slower (decrement). When one of these control signals is applied to the delay line, it is applied to half the elements, either the odd or the even numbered elements. Only one element will have its state changed by the increment or decrement control signal, and it will be the element for which the previous delay's corresponding element is already set or un-set depending upon the applicable case.

Abstract: A method for correcting the duty cycle of a clock signal uses two-dual-slope integrators with two comparators; each comparator is connected to both integrators and configured to include a “dead band” when the input pulse duty cycle is at or near 50%. One comparator detects when duty cycle is high and the other comparator detects when the duty cycle is low. When the duty cycle is within the “dead band” range, neither comparator goes valid. This provides an analog filter where the output comparators will not instantaneously switch between opposite duty cycle correction states. When the duty cycle is greater or less than 50%, the integrated voltages on the two integrators move in opposite directions producing twice the signal magnitude on differential inputs of the comparators, as compared with using a single integrator architecture.

Abstract: A method for correcting the duty cycle of a clock signal uses two-dual-slope integrators with two comparators; each comparator is connected to both integrators and configured to include a “dead band” when the input pulse duty cycle is at or near 50%. One comparator detects when duty cycle is high and the other comparator detects when the duty cycle is low. When the duty cycle is within the “dead band” range, neither comparator goes valid. This provides an analog filter where the output comparators will not instantaneously switch between opposite duty cycle correction states. When the duty cycle is greater or less than 50%, the integrated voltages on the two integrators move in opposite directions producing twice the signal magnitude on differential inputs of the comparators, as compared with using a single integrator architecture.

Abstract: A circuit and technique for reducing parity bit-widths for check bit and syndrome generation is implemented through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The circuit and technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry.

Abstract: A technique for reducing parity bit-widths for check bit and syndrome generation through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry.

Abstract: A short-circuit charge-sharing technique which allows charge-sharing between two or more circuits with a simple shorting transistor controlled to achieve the desired operating voltage levels. The shorting transistor which can be either a P-channel Metal Oxide Semiconductor (PMOS) or an N-channel Metal Oxide Semiconductor (NMOS) device and can be controlled utilizing the same clock that enables the drive of the signals between which charge-sharing occurs. In operation, the desired operating voltage levels can be regulated by increasing and decreasing the pulse width of the control circuit output to the gate of the shorting transistor.

Abstract: A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the present invention, on predetermined input/outputs (I/Os,) data inputs may be inverted to create a desired test pattern (such as data stripes) which are “worst case” for I/O circuitry or column stripes which are “worst case” for memory arrays. A circuit in accordance with the technique of the present invention then matches the pattern for the data out path, inverting the appropriate data outputs to obtain the expected tester data. In this way, the test mode is transparent to any memory tester.

Abstract: A switched capacitor charge sharing technique for integrated circuit devices which allows for efficient charge sharing and signal level generation of exact desired values, and wherein the signal levels of the circuits sharing the charge do not have to have the same voltage levels. In a particular embodiment of the technique of the present invention disclosed herein, a switched capacitor is used to share charge between, for example, two different signals or two different groups of signals. The size of the capacitor can be adjusted to obtain the required signal level of the various signals.

Abstract: A circuit and method provide a charge sharing function during skewed data bus conditions in an integrated circuit memory. The charge sharing circuit includes two additional circuit blocks, one coupled to each of the capacitive lines in the charge-sharing line set, to provide the charge recycling feature. An extra clock signal is active one cycle early during a first clock period to trigger an extra drive circuit to generate a voltage differential on a first capacitive line that is similar to the voltage level generated when real data is being propagated. The presence of an extra voltage signal on the first capacitive line takes place earlier than what would normally happen and allows for proper charge sharing between a second capacitive line and the first capacitive line. Also, there is an additional control signal associated with a last clock period following normal non-skewed charge sharing.

Abstract: A clock distribution tree for an integrated circuit memory includes a set of data drivers, a corresponding set of input buffers coupled to the data drivers, a first clock distribution tree coupled to the data drivers, and a second clock distribution tree coupled to the input buffers, wherein the first and second clock distribution tree are substantially matched and mirrored distribution trees. The line width of the first clock distribution tree is substantially the same as the line width of the second clock distribution tree. The line spacing of the first clock distribution tree is substantially the same as the line spacing of the second clock distribution tree. Numerous topologies for the first and second clock distribution trees can be accommodated, as long as they are matched and mirrored. Valid times for the integrated circuit memory are maximized and data and clock skew is minimized.

Abstract: A charge-sharing circuit includes a first input bus pair, a second input bus pair, and an output bus pair. A capacitor is coupled between a first internal node and a second internal node. A first circuit selectively couples the first internal node to the first input bus pair, the second input bus pair and the output bus pair. A second circuit selectively couples the second internal node to the first input bus pair, the second input bus pair and the output bus pair. A third circuit selectively couples the first input bus pair to a reference voltage. A fourth circuit selectively couples the second input bus pair to the reference voltage. The third circuit is activated when the first input bus pair is inactive and charge is shared between the second bus pair and the output bus pair. The fourth circuit is activated when the second input bus pair is inactive and charge is shared between first bus pair and the output bus pair.

Abstract: A high-speed, static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate data read and write registers and tag blocks. The inclusion of separate data read and write registers allows the device to effectively operate at a cycle time limited only by the DRAM subarray cycle time. Further, the inclusion of two tag blocks allows one to be accessed with an externally supplied address and the other to be accessed with a write-back address, thus eliminating the requirement for a single tag to execute two read-modify write cycles in one DRAM cycle time.

Abstract: A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the present invention, on predetermined input/outputs (I/Os,) data inputs may be inverted to create a desired test pattern (such as data stripes) which are “worst case” for I/O circuitry or column stripes which are “worst case” for memory arrays. A circuit in accordance with the technique of the present invention then matches the pattern for the data out path, inverting the appropriate data outputs to obtain the expected tester data. In this way, the test mode is transparent to any memory tester.

Abstract: An early write with data masking technique for dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM. The technique of the present invention allows for early writes to DRAM arrays with direct bit, byte or word data masking capability.

Abstract: A technique for reducing parity bit-widths for check bit and syndrome generation through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry.

Abstract: A short-circuit charge-sharing technique which allows charge-sharing between two or more circuits with a simple shorting transistor controlled to achieve the desired operating voltage levels. The shorting transistor which can be either a P-channel Metal Oxide Semiconductor (PMOS) or an N-channel Metal Oxide Semiconductor (NMOS) device and can be controlled utilizing the same clock that enables the drive of the signals between which charge-sharing occurs. In operation, the desired operating voltage levels can be regulated by increasing and decreasing the pulse width of the control circuit output to the gate of the shorting transistor.

Abstract: A high-speed, static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate data read and write registers and tag blocks. The inclusion of separate data read and write registers allows the device to effectively operate at a cycle time limited only by the DRAM subarray cycle time. Further, the inclusion of two tag blocks allows one to be accessed with an externally supplied address and the other to be accessed with a write-back address, thus eliminating the requirement for a single tag to execute two read-modify write cycles in one DRAM cycle time.

Abstract: An ECC circuit and method for an integrated circuit memory allows a user to enter a test mode and select a specific location to force a known failure on any memory chip, whether it is fully functional or partially functional. Additional circuitry is placed in the data path where existing buffers and drivers are already located, minimizing any additional speed loss or area penalty required to implement the forced data failure. In a first general method, a logic zero is forced onto a selected data line at a given time. In a second general method, a logic one is forced onto a selected data line at a given time.

Abstract: A clock distribution tree for an integrated circuit memory includes a set of data drivers, a corresponding set of input buffers coupled to the data drivers, a first clock distribution tree coupled to the data drivers, and a second clock distribution tree coupled to the input buffers, wherein the first and second clock distribution tree are substantially matched and mirrored distribution trees. The line width of the first clock distribution tree is substantially the same as the line width of the second clock distribution tree. The line spacing of the first clock distribution tree is substantially the same as the line spacing of the second clock distribution tree. Numerous topologies for the first and second clock distribution trees can be accommodated, as long as they are matched and mirrored. Valid times for the integrated circuit memory are maximized and data and clock skew is minimized.