Abstract: A constant current source is used to provide a constant current to set a delay which defines the period of the output of the oscillator. The delay is preferably set by charging a capacitor with the constant current. Because the current is independent of variations in V.sub.CC and temperature, the capacitor will charge for a given period. Therefore, the frequency or period of oscillation will also be fixed and independent of variation in V.sub.CC or temperature. A current limiting circuit and latch are provided to generate an output which will be transmitted through one or a series of inverters. In an alternate embodiment, a differential amplifier is provided between the delay circuit and the current limiting circuit. This differential amplifier is typically needed in a case where VCC is not well-controlled to provide an output signal which has an appropriate voltage. A method of generating an oscillating output for refreshing a DRAM and a method for refreshing a DRAM are also disclosed.

Abstract: A latch-up protector, and an associated method, for an electronic circuit powered by both a fixed power supply and a pumped power supply. Operation of the latch-up protector prevents the occurrence of latch-up of the circuit during powering-up of the circuit. During powering-up of the electronic circuit, the latch-up protector prevents the application of an input signal to the electronic circuit which might instigate the occurrence of latch-up until the pumped power supply reaches a selected voltage level.

Abstract: An on-chip voltage regulator for controlling a gate of a regulator transistor having a first terminal coupled to receive an external power supply voltage and a second terminal coupled to provide a regulated voltage level to an internal circuit formed on a chip on which the on-chip voltage regulator is formed. The on-chip voltage regulator includes circuitry for detecting when a high current load to which the second terminal of the regulator transistor is coupled is activated. A control transistor is provided having a first terminal coupled to receive the external power supply voltage, a second terminal coupled to the gate of the regulator transistor, and a gate responsive to the means for detecting. In operation, a control voltage with an overshoot portion having preselected duration is generated on the gate of the regulator transistor in response to the activation of the high current load.

Abstract: An integrated circuit having a voltage source and a plurality of conductive power bus tiers extending across the integrated circuit. Each of the power bus tiers are electrically coupled in parallel to the voltage source. The integrated circuit includes a filter capacitor having a first plate and a second plate that are separated by a capacitor dielectric. The first plate forms a bus strap coupling to each of the plurality of power bus tiers.

Abstract: A configurable input device for an integrated circuit having a plurality of input pads, the input device including a plurality of buffers, where each buffer is associated with one of the input pads. Each buffer receives a mode select signal and the buffer is responsive to the mode select signal to place the buffer in an enabled mode or a disabled mode. A receiver portion within each buffer is coupled to the associated input pad. The receiver portion pulls the associated input pad to a preselected logic state while the buffer is in the disabled mode. An output driver within each buffer generates an output signal responsive to a signal on the associated input pad while the buffer is in the enable mode and provides a high impedance while the buffer is in the disabled mode. An output node is coupled to the output drivers of the plurality of buffers.

Abstract: An on-chip voltage regulator for controlling a gate of a regulator transistor having a first terminal coupled to receive an external power supply voltage and a second terminal coupled to provide a regulated voltage level to an internal circuit formed on a chip on which the on-chip voltage regulator is formed. The on-chip voltage regulator includes circuitry for detecting when a high current load to which the second terminal of the regulator transistor is coupled is activated. A control transistor is provided having a first terminal coupled to receive the external power supply voltage, a second terminal coupled to the gate of the regulator transistor, and a gate responsive to the means for detecting. In operation, a control voltage with an overshoot portion having preselected duration is generated on the gate of the regulator transistor in response to the activation of the high current load.

Abstract: A planarized integrated circuit and method for making it are disclosed. The method includes forming portions of a transistor structure that extend to an elevation on an integrated circuit substrate above intermediate regions above the substrate. The portions have an oxide layer on their top surfaces. A layer of polysilicon is formed overall, including in the intermediate regions, to a depth in the intermediate regions larger than the elevation to which the portions of the transistor structure extend. A chemical-mechanical-polishing step is performed on the polysilicon overall to a depth at least extending to the oxide layer on the transistor portions to create a first planarized surface. In subsequent processing, a layer of oxide may be formed over the planarized surface, with source/drain extension regions patterned in the layer of oxide and underlying structures to the surface of the substrate.

Abstract: An integrated circuit having a first and second bond pads, a latch circuit, and a voltage lead. Different configurations of the internal circuitry of the integrated circuit are selected by applying the voltage lead either to the first or second bond pads. This result is achieved because the latch circuit, coupled between the first and second bond pads, is capable of inverting the voltage response seen at the first bond pad.

Abstract: An integrated circuit having a first and second bond pads, a latch circuit, and a voltage lead. Different configurations of the internal circuitry of the integrated circuit are selected by applying the voltage lead either to the first or second bond pads. This result is achieved because the latch circuit, coupled between the first and second bond pads, is capable of inverting the voltage response seen at the first bond pad.

Abstract: A circuit and method for concurrently addressing at least two rows of memory cells of a memory array of a memory device. By concurrently addressing at least two rows of memory cells during testing of the memory device during a burn-in period, the memory device can be tested in a reduced time period.

Abstract: A circuit and method for a memory device, such as a synchronous dynamic random access memory (SDRAM) having at least two memory banks. Columns of at least two memory banks are concurrently addressable to permit data to be written to, or read from, the at least two memory banks concurrently. By writing data concurrently to more than one memory bank, testing of the memory of the memory device can be effectuated in a reduced period of time. Data can also be written or read from a single bank in a multi-bank RAM without requiring that a particular bank be specified during a read/write command.

Abstract: An improved current sensing differential amplifier which includes a separate p-channel bias stage to reduce the minimum operating voltage VCC of the circuit. The separate p-channel bias stage is also used to pre-bias a driver stage to more quickly generate differential output currents. Finally, the improved current sensing differential amplifier also includes negative feedback transistors to improve the recovery time of the circuit.

Abstract: A method and apparatus for compensating for weak elements of a dynamic memory circuit on an integrated circuit chip is disclosed. The method includes identifying weak elements in the memory circuit. The elements may be identified by a known test program, and may be bits, blocks, or other portion of a dynamic memory circuit. The locations of the identified weak elements are programmed into a programmable memory, and the programmed information in the programmable memory is used to refresh the identified weak elements at a different rate from the refresh rate of other bits. This allows an extended or longer refresh interval to be used for the strong elements, while providing adequate refresh for the weak elements, thereby reducing the refresh interval required for the overall memory circuit from the refresh interval which normally would have been used.

Abstract: A wide range power supply for integrated circuits includes a voltage-down converter to receive the input supply voltage and generate a controlled low voltage signal. The circuit also includes a voltage-up converter which receives the controlled low voltage signal to generate a high voltage signal for high power circuits. Finally, a substrate bias generator is employed in the circuit to generate a substrate bias signal. Because the low power voltage is controlled, the high power voltage and the substrate bias signal are independent of any variations in input supply voltage. In alternate embodiments, the voltage-up converter or voltage-down converter can be disabled if the external supply voltage is controlled and maintained in at high or low voltage respectfully.

Abstract: A stress mode circuit is provided to generate a voltage that is either equal to a reference voltage or is a proportion of an external voltage (VCCEXT). The circuit includes two voltage divider circuits to provide the proportion voltage. Two differential amplifiers are provided to generate outputs corresponding to a comparison to the proportion voltage and the reference voltage. The outputs operate switches that couple the reference voltage or the proportion voltage to an output terminal.

Abstract: The voltage reference generator of the present invention includes a plurality of p-channel transistors configured to act as resistors. Switching transistors, responsive to input signals, are utilized to bypass the resistors when in the "on" state, and enable the resistor when in the "off" state. Thus, when enabled, the resistors become part of a total resistance value in a branch of a voltage divider circuit. A minimum amount of space is used on an integrated circuit because the switching transistors are of the same type as the transistors which are configured to act as resistors.

Abstract: A wide range power supply for integrated circuits includes a voltage-down converter to receive the input supply voltage and generate a controlled low voltage signal. The circuit also includes a voltage-up converter which receives the controlled low voltage signal to generate a high voltage signal for high power circuits. Finally, a substrate bias generator is employed in the circuit to generate a substrate bias signal. Because the low power voltage is controlled, the high power voltage and the substrate bias signal are independent of any variations in input supply voltage. In alternate embodiments, the voltage-up converter or voltage-down converter can be disabled if the external supply voltage is controlled and maintained in at high or low voltage respectfully.

Abstract: A counter circuit selectively generates counting sequences in binary and interleave counting modes. A counter is formed by 3 toggle flip-flops. The toggle signals are provided by a toggle control circuit which contains logic gates that are enabled or disabled based on the state of a mode select signal. In binary mode, output bits are permitted to be used to toggle higher order count stages. In interleave mode, the binary toggle signals are blocked, and another counter circuit counts toggle signals in the interleave sequence, which signals are passed by the toggle control circuit to toggle inputs of the main counter. The other counter circuit can be reset in response to a reset signal applied to a load enable input.

Abstract: A constant current source is used to provide a constant current to set a delay which defines the period of the output of the oscillator. The delay is preferably set by charging a capacitor with the constant current. Because the current is independent of variations in V.sub.CC and temperature, the capacitor will charge for a given period. Therefore, the frequency or period of oscillation will also be fixed and independent of variation in V.sub.CC or temperature. A current limiting circuit and latch are provided to generate an output which will be transmitted through one or a series of inverters. In an alternate embodiment, a differential amplifier is provided between the delay circuit and the current limiting circuit. This differential amplifier is typically needed in a case where VCC is not well-controlled to provide an output signal which has an appropriate voltage. A method of generating an oscillating output for refreshing a DRAM and a method for refreshing a DRAM are also disclosed.

Abstract: Positive feedback increases switching speeds and negative feedback prevents the voltage at the inputs from varying too far in a sense amplifier used to sense voltage differentials on bit lines or data lines of semiconductor memories, or elsewhere. Switching speeds improve without increased current consumption.