Abstract: A driver timing and circuit technique for a low noise charge pump circuit of particular applicability with respect to integrated circuit devices requiring voltage levels either more positive than or more negative than, externally supplied voltages. In accordance with the technique of the present invention, the pump capacitor is driven “high” by one transistor and “low” by another. By correctly sizing the devices driving them, each transistor can be turned “off” quickly and “on” slowly and, in an alternative embodiment, both transistors may be “off” at the same time resulting in “tri-state” operation.

Abstract: A shared sense amplifier driver technique for integrated circuit devices including an array of memory cells comprises a plurality of sense amplifiers couplable to the memory cells with each of the sense amplifiers having an associated pull-up and pull-down switching device respectively coupled to a first and second latch node thereof. A first subset of the plurality of sense amplifiers have their first latch node (e.g. latch P-channel “LP”) electrically coupled and a second differing number subset of the plurality of sense amplifiers have their second latch node (e.g. latch N-channel “LN”) electrically coupled. By sharing the selected LP and LN nodes with more than one sense amplifier in a column, “write” recovery time can be significantly improved over that of conventional layouts and designs.

Abstract: A logic circuit has two internal voltage lines and includes additional upper and lower MOS transistors for coupling the external voltage supplies to the internal voltage nodes instead of using a single diode or transistor. These additional devices serve to clamp the internal voltages to a level that minimizes leakage current and maintains the data in the logic circuits.

Abstract: An improved integrated circuit area efficient redundancy multiplexer circuit technique provides similar functionality to conventional CMOS transmission, or “pass” gates while concomitantly reducing circuit complexity, the die area necessary to support redundant elements and complementary control signals in memory device ICs and undesired parasitic capacitance. The technique of the present invention effectuates this end by utilizing the on-chip boosted voltage levels (Vpp) which are generally available in integrated circuit memory devices to supply the voltage for the control signal applied to a single N-channel transistor pass gate instead of the conventional supply voltage level of Vcc. The Vpp voltage and circuit ground (“GND”) are then utilized as the logic “high” and “low” signal levels respectively. This use is made possible due to the fact that these control signals operate at a direct current (“DC”) level after device power-up.

Abstract: A data bus architecture for integrated circuit embedded dynamic random access memory (“DRAM”) having a large aspect ratio (length to width ratio) which serves to reduce power requirements in the data path through the use of multiple metal layers to reduce capacitance on the data busses. This architecture is particularly advantageous for use in addressing data bussing problems inherent in integrated circuit devices having embedded DRAM with a large aspect ratio as well as a relatively large number of input/outputs (“I/Os”) which must be located along one narrow side of the memory. In accordance with the present invention, the memory is divided into multiple sections with data bussing in those sections routed in one metal, or conductive, layer. A different metal layer is used to route global data across these sections to a data register located on one edge of the memory.

Abstract: A read data latch circuit that requires only two phases to execute a data read cycle. The date read lines and data latch lines are precharged and equalized during the data read cycle. A separate phase for equalizing the data latch nodes is eliminated. Rather, the data latch nodes charge share with the previously equalized and precharged data lines. The latch nodes are effectively precharged and equalized, as the capacitance on the data lines is much larger than the capacitance on the data latch nodes.

Abstract: A local write driver circuit for an integrated circuit device memory array which requires only a single write enable signal to couple complimentary data signals between global and local write data lines thereby obviating the need to provide complementary write enable signals as in conventional implementations. By eliminating the need for a second complementary write enable signal line, less on-chip die area is required for the signal path along with a concomitant reduction in power requirements due to the fact that there is one less line which has to switch during a given write cycle.

Abstract: A multi-chip integrated circuit, and an associated method, provides an interface of substantially reduced levels of capacitance and inductance relative to conventional connections formed of bond wires. One of the chips of the integrated circuits comprises a memory device, such as a DRAM, and another of the chips of the integrated circuit is formed of a logic chip, such as a CPU or graphics controller. The memory chip is mounted upon the logic chip utilizing chip-on-chip technology. Because of the reduced levels of capacitance and inductance of the interface connecting the chips together, the resultant integrated circuit can be operated at increased speeds and at reduced levels of power consumption.

Abstract: An architecture for a high speed memory circuit having a relatively large number of internal data lines is shown to include global read and write data lines, and power and ground lines extending laterally across the array. The laterally extending lines are preferably within the third layer of metal. Preferably, the only other metal interconnect over the memory arrays is in the first metal layer, which is used to strap the word lines. Sense amp bands extend longitudinally along the borders of each memory cell bank. Local read and write data lines and read and write column select lines extend through the sense amp bands. Power and ground lines also extend through each sense amp band. Preferably, the architecture includes read path circuitry including a local read circuit that selectively isolates the global read data lines from the local read data lines.

Abstract: The disclosure is directed to a clock doubler circuit for generating a double frequency clock signal from first, second, third and fourth input clock signals. The clock doubler circuit includes four input differential buffers having a relatively low skew path between one of their respective input terminals and their respective output terminals. The clock doubler circuit also includes an exclusive-or logic circuit coupled to the first, second, third and fourth input differential buffers through their respective output terminals. The clock doubler circuit is in the form of three coupled NAND gates, preferably having low skew.

Abstract: A reduced skew write timing scheme for memory circuits is disclosed wherein the signals present on the write data lines and the signals present on the write column select lines are clocked on opposite edges of the clock signal. As a result, the timing sensitivity during writing is relaxed. The duty cycle of the clock is preferably close to fifty percent, most preferably within five percent thereof.

Abstract: A sense amplifier for a very high density integrated circuit memory using CMOS technology is described. Each sense amplifier includes first and second local sense amplifier drive transistors, one connecting the P channel transistors to VCC; the other connecting the N channel transistors to VSS. A read amplifier circuit is provided within each sense amplifier and is operated by read control signals. Internal nodes of the latch of the sense amplifier are coupled by pass transistors that are responsive to column write control signals. Local data write driver transistors are also provided to selectively couple the pass transistors to VCC-Vt or VSS in response to further data write control signals. A relatively wider power line is coupled to the drive transistors to provide VCC thereto, and a narrower line is used to control those first sense amplifier drive transistors.

Abstract: Wordline row redundancy scheme circuitry includes row shift circuitry and row decoder circuitry. If row shift redundancy is not desired, the row shift circuitry applies a first row shift control signal to the row shift control line. If row shift redundancy is desired, the row shift circuit applies a second row shift control signal to the row shift control line. The signal applied to the row shift control line actuates one of first and second electronic switches. Several electronic switches are series-coupled to the first and second electronic switches. The first electronic switch is also series-coupled to a first wordline select line. The second electronic switch is also series-coupled to a second wordline select line adjacent to the first wordline select line. Row address lines are coupled to the several electronic switches to carry row address selection control signals that selectively actuate its electronic switch.

Abstract: A sense amplifier for a very high density integrated circuit memory using CMOS technology is described. Each sense amplifier includes first and second local sense amplifier drive transistors, one connecting the P channel transistors to VCC; the other connecting the N channel transistors to VSS. A read amplifier circuit is provided within each sense amplifier and is operated by read control signals. Internal nodes of the latch of the sense amplifier are coupled by pass transistors that are responsive to column write control signals. Local data write driver transistors are also provided to selectively couple the pass transistors to VCC-Vt or VSS in response to further data write control signals. A relatively wider power line is coupled to the drive transistors to provide VCC thereto, and a narrower line is used to control those first sense amplifier drive transistors.

Abstract: A sense amplifier for a very high density integrated circuit memory using CMOS technology is described. Each sense amplifier includes first and second local sense amplifier drive transistors, one connecting the P channel transistors to VCC; the other connecting the N channel transistors to VSS. A read amplifier circuit is provided within each sense amplifier and is operated by read control signals. Internal nodes of the latch of the sense amplifier are coupled by pass transistors that are responsive to column write control signals. Local data write driver transistors are also provided to selectively couple the pass transistors to VCC-Vt or VSS in response to further data write control signals. A relatively wider power line is coupled to the drive transistors to provide VCC thereto, and a narrower line is used to control those first sense amplifier drive transistors.

Abstract: A technique for integrating an internal clock signal with various function commands in an integrated circuit device having an externally supplied clock signal to create a set of command clocks which have the same rising (or falling) edge time, duty cycle and duration and are, therefore, inherently clocked to ameliorate signal “race” and “skew” conditions encountered in prior designs. The technique of the present invention, therefore, improves overall device operational speeds in executing commands by reducing internal gate delays and resulting in faster data access times in integrated circuit memory devices such as synchronous dynamic random access memory (“SDRAM”) devices. Moreover, because the resultant design provides faster operation times, lower cost process technologies may be utilized to achieve substantially comparable performance levels.

Abstract: A memory device including a plurality of sense amplifiers distributed about an integrated circuit chip, where each sense amplifier has a power node for receiving current. A conductor couples the power nodes of a number of sense amplifiers together. A low-impedance power supply conductor extends to each sense amplifier and a local drive transistor is provided for each sense amplifier. A timer unit generates an output signal controlling the local drive transistors. A first component within the timer unit causes the output to change from a first logic level towards a second logic level at a first rate while a second component within the timer unit causes the output to change at a second rate, wherein the second rate is greater than the first rate.

Abstract: A current sensing differential amplifier with high rejection of power supply variations and method for an integrated circuit memory device which allows the amplifier's differential voltage level and speed to track that of the sense amplifier supplying the information, thereby achieving the needed margin for critical synchronous timing. The reliability of the differential amplifier is also increased due to the provision of a larger differential signal and higher supply voltage levels. In a preferred embodiment, an n-channel transistor serves as a regulator with its drain terminal coupled to an unregulated supply voltage source ("V.sub.cc "). The gate of the transistor is then coupled to a regulated supply voltage ("V.sub.ccp ") which is a function of the voltage supply for the sense amplifier. The source of the transistor is connected to the sources of the p-channel transistors in the main amplifier which provide feedback to the main amplifier.

Abstract: A sense amplifier for a very high density integrated circuit memory using CMOS technology is described. Each sense amplifier includes first and second local sense amplifier drive transistors, one connecting the P channel transistors to VCC; the other connecting the N channel transistors to VSS. A read amplifier circuit is provided within each sense amplifier and is operated by read control signals. Internal nodes of the latch of the sense amplifier are coupled by pass transistors that are responsive to column write control signals. Local data write driver transistors are also provided to selectively couple the pass transistors to VCC-Vt or VSS in response to further data write control signals. A relatively wider power line is coupled to the drive transistors to provide VCC thereto, and a narrower line is used to control those first sense amplifier drive transistors.

Abstract: A receiver circuit for an integrated circuit including an input buffer having an input coupled to receive an external input signal and an output coupled to generate a buffered input signal in response to the external input signal. The input buffer is selectively enabled by a control signal. A latch is coupled to receive the buffered input signal and to generate a latched output signal. A delay circuit is coupled to receive the latched output signal and to generate a delayed signal. A comparator is coupled to receive both the latched output signal and the delayed signal. The comparator has an output coupled to the input buffer to generate the control signal.