Intel Patents
Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.
Intel Patents by Type- Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
- Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
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Publication number: 20240137185Abstract: This disclosure describes systems, methods, and devices related to WLAN sensing sounding. A device may identify a sensing null data packet (NDP) request frame received from a second device, the sensing NDP request frame associated with performing a wireless local area network channel sounding procedure; identify transmit parameters included in a transmit control field of the sensing NDP request frame; generate an NDP frame using the transmit parameters; and send, in response to the sensing NDP request frame, the NDP frame to the second device.Type: ApplicationFiled: December 29, 2023Publication date: April 25, 2024Applicant: Intel CorporationInventors: Claudio Da Silva, Cheng Chen, Bahareh Sadeghi, Carlos Cordeiro
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Publication number: 20240136277Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.Type: ApplicationFiled: December 22, 2023Publication date: April 25, 2024Applicant: Intel CorporationInventors: Gilbert Dewey, Ryan Keech, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal, Willy Rachmady, Anand Murthy
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Publication number: 20240134604Abstract: Described herein is a generalized optimal reduction scheme for reducing an array modulo a constant. The constant modulo operation calculates a result for array of bits xi, width n modulo an odd positive integer constant d, (e.g., x[n:0] mod d). Circuitry to perform such operation can be configured to compress the array of bits xi, width n into an array of bits yi width m. The techniques described herein enable the design of optimal circuitry via iterative exploration of all potential reduction strategies that are available given the input constraints.Type: ApplicationFiled: December 26, 2023Publication date: April 25, 2024Applicant: Intel CorporationInventors: Theo Drane, Christopher Louis Poole, William Zorn, Emiliano Morini
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Publication number: 20240136279Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device, and integrated inductors formed over the semiconductor devices. Power delivery to the device is on the opposite side of the semiconductor devices. The integrated inductors may be used for power step-down to reduce device thickness and/or a number of power rails.Type: ApplicationFiled: October 24, 2022Publication date: April 25, 2024Applicant: Intel CorporationInventors: Min Suet Lim, Telesphor Kamgaing, Chee Kheong Yoon, Chu Aun Lim, Eng Huat Goh, Jooi Wah Wong, Kavitha Nagarajan
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Publication number: 20240134719Abstract: Embodiments described herein provide a technique to facilitate the synchronization of workgroups executed on multiple graphics cores of a graphics core cluster. One embodiment provides a graphics core including a cache memory and a graphics core coupled with the cache memory. The graphics core includes execution resources to execute an instruction via a plurality of hardware threads and barrier circuitry to synchronize execution of the plurality of hardware threads, wherein the barrier circuitry is configured to provide a plurality of re-usable named barriers.Type: ApplicationFiled: October 24, 2022Publication date: April 25, 2024Applicant: Intel CorporationInventors: Fangwen Fu, Chunhui Mei, John A. Wiegert, Yongsheng Liu, Ben J. Ashbaugh
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Publication number: 20240138133Abstract: The disclosure is directed to apparatus and methods for manufacturing including a collaborative robot, a camera operatively coupled to the collaborative robot, a memory coupled to the collaborative robot, and processing circuitry coupled to the memory, the processing circuitry configured to receive image data of at least one component intended for a printed circuit board (PCB), the image data collected by the camera operatively coupled to the collaborative robot, determine, based on the image data, a coordinate location for the component, and secure the component to the PCB using an end effector of the collaborative robot based on the received image data. In one embodiment, the collaborative robot is configured to operate alongside a human, the collaborative robot in combination with the camera configured to manufacture a computer system with the PCB.Type: ApplicationFiled: October 23, 2022Publication date: April 25, 2024Applicant: Intel CorporationInventor: Shoghi Effendi RAJAGOPAL
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Publication number: 20240135076Abstract: Described herein is a technique for automatic program code optimization for high-level synthesis. One embodiment provides a method comprising receiving input including first program code in a high-level language; translating the first program code into an intermediate language; constructing an equality graph (e-graph) from the intermediate language; interleaving control-flow, data path, and gate-level transformations to explore equivalent hardware designs represented by the e-graph; selecting a hardware design based on a cost function; extracting a representation of a selected hardware design in the intermediate language; generating second program code in the high-level language; and performing high-level synthesis using the second program code.Type: ApplicationFiled: December 26, 2023Publication date: April 25, 2024Applicant: Intel CorporationInventors: Jianyi Cheng, Samuel Coward, Lorenzo Chelini, Rafael Barbalho, Theo Drane
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Publication number: 20240138006Abstract: This disclosure describes systems, methods, and devices related to adding or removing communication access points (APs) affiliated with an associated AP multi-link device (AP-MLD). A non-AP-MLD may identify a communication link between the non-AP-MLD and an AP-MLD, the communication link previously used by the non-AP-MLD; encode a request frame comprising a multi-link reconfiguration element indicative of a request to add or remove the communication link; cause the non-AP-MLD to transmit the request frame to the AP-MLD; and identify a response frame received from the AP-MLD, the response frame comprising the multi-link reconfiguration element and indicating whether the communication link was accepted or rejected to be added or removed.Type: ApplicationFiled: December 29, 2023Publication date: April 25, 2024Applicant: Intel CorporationInventors: Po-Kai Huang, Ido Ouzieli, Danny Alexander, Daniel Bravo, Laurent Cariou
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Publication number: 20240134797Abstract: Embodiments described herein provide a technique to facilitate the broadcast or multicast of asynchronous loads to shared local memory of a plurality of graphics cores within a graphics core cluster. One embodiment provides a graphics processor including a cache memory a graphics core cluster coupled with the cache memory. The graphics core cluster includes a plurality of graphics cores. The plurality of graphics cores includes a graphics core configured to receive a designation as a producer graphics core for a multicast load, read data from the cache memory; and transmit the data read from the cache memory to a consumer graphics core of the plurality of graphics cores.Type: ApplicationFiled: October 24, 2022Publication date: April 25, 2024Applicant: Intel CorporationInventors: John A. Wiegert, Joydeep Ray, Vasanth Ranganathan, Biju George, Fangwen Fu, Abhishek R. Appu, Chunhui Mei, Changwon Rhee
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Publication number: 20240134603Abstract: The techniques described in the detailed description above enable the manufacturing of circuits with increased performance and efficiency when performing division by a constant number. One embodiment provides circuitry including an input circuit to receive an input value including a plurality of bits, a logarithmic tree coupled with the input circuit, the logarithmic tree configured to compute an array of values based on a plurality of multi-bit groups of the plurality of bits of the input value, each value in the array of values includes a modulus of a corresponding multi-bit group with respect to the constant, a binary array adder to compute a quotient of the division operation based on the array of values, the input value, and the constant, and an output circuit to output the quotient.Type: ApplicationFiled: December 26, 2023Publication date: April 25, 2024Applicant: Intel CorporationInventors: Theo Drane, Christopher Louis Poole, William Zorn, Emiliano Morini
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Publication number: 20240134803Abstract: An embodiment of an integrated circuit may comprise an array of hardware counters, and circuitry communicatively coupled to the array of hardware counters, the circuitry to count accesses to one or more selected pages of a memory with the array of hardware counters. Other embodiments are disclosed and claimed.Type: ApplicationFiled: March 24, 2021Publication date: April 25, 2024Applicant: Intel CorporationInventors: Sanjay Kumar, Phillip Lantz, Rajesh Sankaran, David Hansen, Evgeny V. Voevodin, Andrew Anderson, Lizhen You, Xin Zhou, Nikhil Talpallikar
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Publication number: 20240134527Abstract: Embodiments described herein provide a technique to enable access to entries in a surface state or sampler state using 64-bit virtual addresses. One embodiment provides a graphics core that includes memory access circuitry configured to facilitate access to the memory by functional units of the graphics core. The memory access circuitry is configured to receive a message to access an entry in a surface state or a sampler state associated with a parallel processing operation. The message specifies a base address for a surface state entry or sampler state entry. The circuitry can add the base address and the offset to determine a 64-bit virtual address for the entry in the surface state entry or the sampler state and submit a memory access request to the memory to access the entry of the surface state or sampler state.Type: ApplicationFiled: October 20, 2022Publication date: April 25, 2024Applicant: Intel CorporationInventors: Joydeep Ray, Michael Apodaca, Yoav Harel, Guei-Yuan Lueh, John A. Wiegert
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Publication number: 20240134804Abstract: An apparatus comprising translator circuitry to receive a plurality of physical addresses of memory data, determine an offset associated with each of the physical page addresses and apply a tweak seed to each offset to generate a plurality of tweaks.Type: ApplicationFiled: October 18, 2022Publication date: April 25, 2024Applicant: Intel CorporationInventors: Marcin Andrzej Chrapek, Reshma Lal
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Publication number: 20240133799Abstract: This disclosure describes systems, methods, and devices related to bond strength measurement. A device may comprise a first portion of a plate connected to a movement mechanism, a second portion of the plate comprising a sticky probe and a third portion of the plate comprising a mirror with a reflective side pointing outwards. The device may further comprise an optical fiber sensor assembly comprising an optical fiber bundle for sending light through a first optical fiber and receiving light reflected from the mirror through a second optical fiber.Type: ApplicationFiled: October 24, 2022Publication date: April 25, 2024Applicant: Intel CorporationInventor: Khaled AHMED
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Publication number: 20240136323Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Applicant: Intel CorporationInventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan, Arun Chandrasekhar
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Publication number: 20240133718Abstract: The disclosure is directed to apparatus and methods for detection of out of position (OOP) components in a carrier tape forming machine. An apparatus includes cross track sensors coupled to the bus interface circuitry, the cross track sensors configured to detect OOP components prior to overlaying the components on the carrier tape with cover tape, optical sensors to detect the OOP components on the carrier tape after overlaying with cover tape and prior to sealing and to detect reflections from OOP components seated on the carrier tape, an amplifier coupled to the optical sensors to amplify signals generated by the optical sensors and set a range for determining whether the components are OOP, and relays to receive indications of detected OOP components, and a controller coupled to the relays to stop the carrier tape forming machine as a function of signals received by the relays.Type: ApplicationFiled: October 19, 2022Publication date: April 25, 2024Applicant: Intel CorporationInventors: Ngoc Duy VU, Nguyen Hoang Tan LE, Minh Anh Khoa NGUYEN
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Publication number: 20240135209Abstract: A first computing system includes a data store with a sensitive dataset. The first computing system uses a feature extraction tool to perform a statistical analysis of the dataset to generate feature description data to describe a set of features within the dataset. A second computing system is coupled to the first computing system and does not have access to the dataset. The second computing system uses a data synthesizer to receive the feature description data and generate a synthetic dataset that models the dataset and includes the set of features. The second computing system trains a machine learning model with the synthetic data set and provides the trained machine learning model to the first computing system for use with data from the data store as an input.Type: ApplicationFiled: December 29, 2023Publication date: April 25, 2024Applicant: Intel CorporationInventors: Priyanka Mudgal, Rita H. Wouhaybi
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Publication number: 20240135750Abstract: An initializer for circle distribution on a 2D surface using a polar coordinate system for image compression, video compression, motion detection, and posture detection. The initializer can also be used for sphere distribution in a 3D shape. The initializer uses a mixed deterministic and iterative/stochastic approach. Using the polar coordinate system for initialization enables coverage of the user space, and after parameters are initialized, the method transitions to a cartesian coordinate system. Methods for using the polar system in CPU units by applying an XNOR/AND architecture for neural network model compression are also described. The neural network includes a perceptron for supervised learning of binary classifiers. The unit responsible for multiplication in a MAC architecture can be replaced with a non-linear expressive function. Thus, a neural network having a non-linear expressive perceptron (quadtron) is described for solving circle distribution and other problems.Type: ApplicationFiled: November 16, 2023Publication date: April 25, 2024Applicant: Intel CorporationInventors: Pawel Tomkiewicz, Pawel Zielonka, Lukasz Braszka, Monica Lucia Martinez-Canales
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Patent number: 11966860Abstract: Disclosed examples include after a first tuning of hyperparameters in a hyperparameter space, selecting first hyperparameter values for respective ones of the hyperparameters; generating a polygonal shaped failure region in the hyperparameter space based on the first hyperparameter values; setting the first hyperparameter values to failure before a second tuning of the hyperparameters; and selecting second hyperparameter values for the respective ones of the hyperparameters in a second tuning region after the second tuning of the hyperparameters in the second tuning region, the second tuning region separate from the polygonal shaped failure region.Type: GrantFiled: March 4, 2022Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Kevin Tee, Michael McCourt, Patrick Hayes, Scott Clark
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Patent number: 11966281Abstract: Systems, methods, and devices for isolating a misbehaving accelerator circuit, such as an accelerator function unit or an accelerated function context, are provided. An integrated circuit may include a region that includes an accelerator circuit. When the accelerator circuit issues a request, another region of the integrated circuit or a processor connected to the integrated circuit may determine whether there is a misbehavior associated with the request and, in response to determining that there is a misbehavior associated with the request, may perform a misbehavior response to mitigate a negative impact of the misbehavior of the accelerator circuit.Type: GrantFiled: April 18, 2022Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Sundar Nadathur, Pratik M. Marolia, Henry M. Mitchel, Joseph J. Grecco, Utkarsh Y. Kakaiya, David A. Munday
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Patent number: 11966268Abstract: Apparatus and methods for thermal management of electronic user devices are disclosed herein. An example apparatus includes at least one of a user presence detection analyzer to identify a presence of a user relative to an electronic device based on first sensor data generated by a first sensor or at least one of an image data analyzer or a motion data analyzer to determine a gesture of the user relative to the device based on second sensor data generated by a second sensor; a thermal constraint selector to select a thermal constraint for a temperature of an exterior surface of the electronic device based on one or more of the presence of the user or the gesture; and a power source manager to adjust a power level for a processor of the electronic device based on the thermal constraint.Type: GrantFiled: April 28, 2022Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Columbia Mishra, Carin Ruiz, Helin Cao, Soethiha Soe, James Hermerding, II, Bijendra Singh, Navneet Singh
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Patent number: 11966681Abstract: The computer executable instructions include a command that accepts multiple user input through various command options. The command encapsulates and implements multiple original software algorithms that convert trunking design intent, expressed via the command options, into trunks on multiple layers of a process technology node. Once executed, the command generates shapes of trunks of specified topology on specified layers. The command includes a set of options to generate a simple or complex trunking topology. The command accepts topology, set of zones, nets and many other options that the user provides to the command to yield trunks of a desired topology. The topology description is relative; thus, it can easily adjust as design changes. The command together with its options represents trunk creation intent.Type: GrantFiled: August 25, 2020Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Sergei Babokhov, Charles Magnuson
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Patent number: 11966503Abstract: Systems, apparatuses, and methods to mitigate effects of glitch attacks on a broadcast communication bus are provided. The voltage levels of the communication bus are repeatedly sampled to identify glitch attacks. The voltage level on the communication bus can be overdriven or overwritten to either corrupt received messages or correct received messages.Type: GrantFiled: September 24, 2021Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Marcio Juliato, Vuk Lesi, Christopher Gutierrez, Shabbir Ahmed, Qian Wang, Manoj Sastry
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Patent number: 11966286Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.Type: GrantFiled: April 7, 2022Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Kuljit S. Bains, Rajat Agarwal, Jongwon Lee
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Patent number: 11966334Abstract: Systems, methods, and apparatuses relating to linear address masking architecture are described. In one embodiment, a hardware processor includes an address generation unit to generate a linear address for a memory access request to a memory, at least one control register comprising a user mode masking bit and a supervisor mode masking bit, a register comprising a current privilege level indication, and a memory management unit to mask out a proper subset of bits inside an address space of the linear address for the memory access request based on the current privilege level indication and either of the user mode masking bit or the supervisor mode masking bit to produce a resultant linear address, and output the resultant linear address.Type: GrantFiled: January 11, 2021Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Ron Gabor, Igor Yanover
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Patent number: 11967086Abstract: A method for trajectory generation based on player tracking is described herein. The method includes determining a temporal association for a first player in a captured field of view and determining a spatial association for the first player. The method also includes deriving a global player identification based on the temporal association and the spatial association and generating a trajectory based on the global player identification.Type: GrantFiled: July 31, 2019Date of Patent: April 23, 2024Assignee: INTEL CORPORATIONInventors: Yikai Fang, Qiang Li, Wenlong Li, Chenning Liu, Chen Ling, Hongzhi Tao, Yumeng Wang, Hang Zheng
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Patent number: 11966742Abstract: Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.Type: GrantFiled: May 3, 2023Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Eliezer Weissmann, Mark Charney, Michael Mishaeli, Robert Valentine, Itai Ravid, Jason W. Brandt, Gilbert Neiger, Baruch Chaikin, Efraim Rotem
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Patent number: 11966998Abstract: Examples described herein relate to a graphics processing apparatus that includes a memory device and a graphics processing unit (GPU). In some examples, the GPU is configured to execute a shader program that is to identify at least two code blocks that are independent from each other and cause execution of an unexecuted independent code block with available data based on use of a scoreboard to track data availability for independent code blocks. In some examples, execution of the shader program is to cause the GPU to select a first code block identifier for tracking completion of a dependency of the first independent code block. In some examples, execution of the shader program is to cause the GPU to identify an offset to a first instruction position in a sequence of instructions of the first independent code block in an instruction queue.Type: GrantFiled: May 27, 2020Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Rafal Rudnicki, Przemyslaw Szymanski
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Patent number: 11966473Abstract: Methods, apparatus, systems and articles of manufacture to identify a side-channel attack are disclosed. Example instructions cause one or more processors to generate an event vector based on one or more counts corresponding to tasks performed by a central processing unit; determine distances between the event vector and weight vectors of neurons in a self-organizing map; select a neuron of the neurons that results based on a determined distance; identify neurons that neighbor the selected neuron; and update at least one of a weight vector of the selected neuron or weight vectors of the neighboring neurons based on the determined distance of the selected neuron.Type: GrantFiled: July 26, 2021Date of Patent: April 23, 2024Assignee: INTEL CORPORATIONInventors: Mohammad Mejbah Ul Alam, Justin Gottschlich, Shengtian Zhou
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Patent number: 11966330Abstract: Examples described herein relate to processor circuitry to issue a cache coherence message to a central processing unit (CPU) cluster by selection of a target cluster and issuance of the request to the target cluster, wherein the target cluster comprises the cluster or the target cluster is directly connected to the cluster. In some examples, the selected target cluster is associated with a minimum number of die boundary traversals. In some examples, the processor circuitry is to read an address range for the cluster to identify the target cluster using a single range check over memory regions including local and remote clusters. In some examples, issuance of the cache coherence message to a cluster is to cause the cache coherence message to traverse one or more die interconnections to reach the target cluster.Type: GrantFiled: June 5, 2020Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Vinit Mathew Abraham, Jeffrey D. Chamberlain, Yen-Cheng Liu, Eswaramoorthi Nallusamy, Soumya S. Eachempati
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Patent number: 11967129Abstract: Apparatuses, methods and storage medium associated with multi-camera devices are disclosed herein. In embodiments, a multi-camera device may include 3 or more camera sensors disposed on a world facing side of the multi-camera device. Further, the multi-camera device may be configured to provide a soft shutter button at a location on an opposite side to the world facing side, coordinated with locations of the 3 or more camera sensors that reduces likelihood of blocking of one or more of the 3 or more camera sensors. Other embodiments may be disclosed or claimed.Type: GrantFiled: February 28, 2022Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Russell S. Love, Peter W. Winer, James Granger, Gerald A. Pham, Ka-Kei Wong, Varun Nasery, Kabeer R. Manchanda, Yu-Tseh Chi, Ali Mehdizadeh
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Patent number: 11966843Abstract: Methods, apparatus, systems and articles of manufacture for distributed training of a neural network are disclosed. An example apparatus includes a neural network trainer to select a plurality of training data items from a training data set based on a toggle rate of each item in the training data set. A neural network parameter memory is to store neural network training parameters. A neural network processor is to generate training data results from distributed training over multiple nodes of the neural network using the selected training data items and the neural network training parameters. The neural network trainer is to synchronize the training data results and to update the neural network training parameters.Type: GrantFiled: June 13, 2022Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Meenakshi Arunachalam, Arun Tejusve Raghunath Rajan, Deepthi Karkada, Adam Procter, Vikram Saletore
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Patent number: 11967580Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.Type: GrantFiled: September 29, 2022Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Adel A. Elsherbini, Amr Elshazly, Arun Chandrasekhar, Shawna M. Liff, Johanna M. Swan
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Patent number: 11967615Abstract: Embodiments of the present invention are directed to dual threshold voltage (VT) channel devices and their methods of fabrication. In an example, a semiconductor device includes a gate stack disposed on a substrate, the substrate having a first lattice constant. A source region and a drain region are formed on opposite sides of the gate electrode. A channel region is disposed beneath the gate stack and between the source region and the drain region. The source region is disposed in a first recess having a first depth and the drain region disposed in a second recess having a second depth. The first recess is deeper than the second recess. A semiconductor material having a second lattice constant different than the first lattice constant is disposed in the first recess and the second recess.Type: GrantFiled: December 23, 2015Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Hsu-Yu Chang, Neville L. Dias, Walid M. Hafez, Chia-Hong Jan, Roman W. Olac-Vaw, Chen-Guan Lee
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Patent number: 11967980Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.Type: GrantFiled: August 4, 2021Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Ashoke Ravi, Benjamin Jann, Satwik Patnaik
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Patent number: 11968689Abstract: Methods, systems, and storage media are described for monitoring downlink control information (DCI). In particular, some embodiments may be directed to monitoring DCI for an indication of channel occupancy time (COT) information. Other embodiments may be described and/or claimed.Type: GrantFiled: May 31, 2022Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Yongjun Kwak, Bishwarup Mondal, Daewon Lee, Hwan-Joon Kwon, Lopamudra Kundu, Hong He
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Patent number: 11968380Abstract: An apparatus for encoding and decoding video receives a request to decode a current video frame. The apparatus determines whether encoding is within a threshold for a previous video frame. Additionally, the apparatus waits for the encoding to start if the encoding is within the threshold. Further, the apparatus provides a signal to begin encoding the current video frame. Also, the apparatus submits a decode workload to a graphics processor unit (GPU) for the current video frame. The apparatus additionally submits, in parallel with submitting the decode workload to the GPU, an encode workload to the GPU for the previous video frame.Type: GrantFiled: June 29, 2016Date of Patent: April 23, 2024Assignee: INTEL CORPORATIONInventors: Jiaping Wu, Kin-Hang Cheung, Bo Zhao
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Patent number: 11968559Abstract: A device to host a service producer in a 5G system (or 5G system architecture), a method to be performed at the device, and a non-transitory storage device storing instructions to be executed at the device. The method includes: decoding a request from a service consumer to manage one or more 5G quality of service (QoS) indicators (5QIs), each 5QI including a 5QI value and corresponding 5QI characteristics; configuring one or more network functions (NFs) of the 5GS with the 5QIs based on the request; and encoding for transmission to the service consumer a message including a result of managing the one or more 5QIs.Type: GrantFiled: May 14, 2021Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Yizhi Yao, Joey Chou
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Publication number: 20240130068Abstract: Technologies for a flexible three-dimensional power plane in a chassis are disclosed. In one embodiment, a flexible ribbon cable is laid along a circuit board tray. The flexible ribbon cable is secured to the tray using power bosses. The power bosses connect to one or more conductors on the ribbon cable. When the circuit board is mounted on the circuit board tray, the power bosses extend through holes in the circuit board and mate with power clips on the surface of the circuit board tray. The ribbon cable, power bosses, and power clips can distribute power to various locations on the circuit board, without requiring large traces that take up space on the circuit board.Type: ApplicationFiled: December 28, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Nan Wang, Zhichao Z. Zhang, Lihui Wu, Jialiang Xu, Xiaoguo Liang, Bo Chen, Haifeng Gong
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Publication number: 20240130002Abstract: Various technologies relating to wireless sensor networks (WSNs) are disclosed, including, but not limited to, device onboarding and authentication, network association and synchronization, data logging and reporting, asset tracking, and automated flight state detection.Type: ApplicationFiled: March 3, 2022Publication date: April 18, 2024Applicant: Intel CorporationInventors: Rahul Khanna, Yi Qian, Greeshma Pisharody, Raju Arvind, Jiejie Wang, Laura M. Rumbel, Christopher R. Carlson, Jennifer M. Williams, Prince Adu Agyeman
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Publication number: 20240128181Abstract: Embodiments of a microelectronic assembly that includes: a package substrate comprising a plurality of layers of organic dielectric material and conductive traces alternating with conductive vias in alternate layers of the organic dielectric material; and a plurality of integrated circuit dies coupled to a first side of the package substrate by interconnects, in which: the plurality of layers of the organic dielectric material comprises at least a first layer having a conductive via and a second layer having a conductive trace in contact with the conductive via, the second layer is not coplanar with the first layer, sidewalls of the conductive via are orthogonal to the conductive trace, and two opposing sidewalls of the conductive via separated by a width of the conductive via protrude from respectively proximate edges of the conductive trace by a protrusion that is at least ten times less than the width of the conductive via.Type: ApplicationFiled: October 17, 2022Publication date: April 18, 2024Applicant: Intel CorporationInventors: Jeremy Ecton, Brandon C. Marin, Srinivas V. Pietambaram, Hiroki Tanaka, Haobo Chen
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Publication number: 20240126615Abstract: Embodiments for orchestrating execution of workloads on a distributed computing infrastructure are disclosed herein. In one example, environment data is received for compute devices in a distributed computing infrastructure. The environment data is indicative of an operating environment of the respective compute devices and a physical environment of the respective locations of the compute devices. Future operating conditions of the compute devices are predicted based on the environment data, and workloads are orchestrated for execution on the distributed computing infrastructure based on the predicted future operating conditions.Type: ApplicationFiled: December 13, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Sundar Nadathur, Akhilesh Thyagaturu, Jonathan L. Kyle, Scott M. Baker, Woojoong Kim
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Publication number: 20240126357Abstract: Embodiments provided a blend circuit configured to perform a power optimized blend using blend circuitry configured such that the dynamic power consumed during the blending of two input color values is reduced when the input colors are close in value. When blending two identical input color values, a portion of the blend circuit can be bypassed and clock and/or data gated.Type: ApplicationFiled: December 20, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventor: Theo Drane
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Publication number: 20240126964Abstract: Described herein is a technique for automated detection of case-splitting opportunities in RTL. The techniques described herein facilitate the integration of case-splitting into a hardware design tool flow, allowing the generation of hardware designs that do not suffer from timing violations. One embodiment provides a method comprising analyzing a first hardware description in a hardware description language to identify a critical path in a circuit represented by the hardware description, automatically detecting a case-splitting opportunity within the critical path, generating hardware description language for a case split having determined operator domain restrictions, and outputting a second hardware description including the hardware description language for the case split, wherein the second hardware description has a reduced operator hardware cost for the critical path relative to the first hardware description.Type: ApplicationFiled: December 22, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Samuel Coward, Theo Drane, George A. Constantinides
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Publication number: 20240126691Abstract: Technologies for cryptographic separation of MMIO operations with an accelerator device include a computing device having a processor and an accelerator. The processor establishes a trusted execution environment. The accelerator determines, based on a target memory address, a first memory address range associated with the memory-mapped I/O transaction, generates a second authentication tag using a first cryptographic key from a set of cryptographic keys, wherein the first key is uniquely associated with the first memory address range. An accelerator validator determines whether the first authentication tag matches the second authentication tag, and a memory mapper commits the memory-mapped I/O transaction in response to a determination that the first authentication tag matches the second authentication tag. Other embodiments are described and claimed.Type: ApplicationFiled: September 7, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Luis S. Kida, Reshma Lal, Soham Jayesh Desai
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Publication number: 20240126695Abstract: Various embodiments are generally directed to virtualized systems. A first guest memory page may be identified based at least in part on a number of accesses to a page table entry for the first guest memory page in a page table by an application executing in a virtual machine (VM) on the processor, the first guest memory page corresponding to a first byte-addressable memory. The execution of the VM and the application on the processor may be paused. The first guest memory page may be migrated to a target memory page in a second byte-addressable memory, the target memory page comprising one of a target host memory page and a target guest memory page, the second byte-addressable memory having an access speed faster than an access speed of the first byte-addressable memory.Type: ApplicationFiled: December 21, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Yao Zu DONG, Kun TIAN, Fengguang WU, Jingqi LIU
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Publication number: 20240128138Abstract: Semiconductor packages and methods for forming semiconductor packages are disclosed. An example semiconductor package includes a substrate and a core. An insulator material is present over the core, and along a direction perpendicular to a first surface of the core, a portion of the insulator material is between the core and a first surface of the substrate. A via extends between the first surface of the core and a second surface of the core in the direction perpendicular to the first surface of the core. A bridge die is in a recess in the substrate. The bridge die is coupled with the via. An electronic component is coupled to an end of the via at a second surface of the substrate.Type: ApplicationFiled: December 21, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Robert L. Sankman, Rahul N. Manepalli, Robert Alan May, Srinivas Venkata Ramanuja Pietambaram, Bharat P. Penmecha
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Publication number: 20240126967Abstract: Described herein are techniques to automatically create a software model which covers the core functionality of a semiconductor design to be formally verified and can be easily consumed by a formal verification tool for software or semiconductor designs. These techniques enable verification engineers to expand the scope of formal verification to fix both software and RTL bugs, saving significant design time and reducing the time to market of for new products.Type: ApplicationFiled: December 22, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Disha Puri, Sparsa Roychowdhury, Geethabai Biradar, Theo Drane, Achutha Kiran Kumar M V
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Publication number: 20240129944Abstract: For example, a wireless communication device may be configured to determine an expected interference-based value corresponding to an Uplink (UL) transmission from a wireless communication station (STA) in a Trigger-Based (TB) Multi-User (MU) UL transmission to be communicated from a plurality of STAs to the wireless communication device; to determine one or more transmit (Tx) configuration parameters for the STA based on the expected interference-based value corresponding to the UL transmission from the STA; and to transmit a trigger frame to trigger the TB MU UL transmission, the trigger frame including the one or more Tx configuration parameters to configure the UL transmission from the STA.Type: ApplicationFiled: December 28, 2023Publication date: April 18, 2024Applicant: INTEL CORPORATIONInventors: Alexander W. Min, Arik Klein, Rath Vannithamby, Ziv Avital
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Patent number: D1023975Type: GrantFiled: July 12, 2021Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Samantha Rao, Harish Jagadish, Arvind S