Abstract: A method for generating a clock signal by a phase-locked loop includes generating a phase difference signal based on an input clock signal and a feedback clock signal and generating a loop filter output signal. In a first mode, the loop filter output signal is generated based on the phase difference signal and a predetermined frequency slope, and may include generating a phase-slope-limited version of the phase difference signal based on a predetermined phase slope limit and generating a frequency-slope-limited version of the phase difference signal based on the predetermined frequency slope limit. In a second mode, the loop filter output signal may be generated based on the predetermined frequency slope limit, a value of the loop filter output signal, and a target frequency. In the second mode, the loop filter output signal may be generated further based on a predetermined frequency step value.

Abstract: A TAF-DPS based circuits and methods to improve electronic system's frequency accuracy and enhance its frequency stability is disclosed in this application. Present invention creates a circuit architecture and a calculation scheme for compensating frequency source's frequency error. Present invention further discloses a method of incorporating said scheme into functional chip built in either ASIC or FPGA fashion. Present invention further presents a method of using TAF-DPS-frequency-compensation-scheme-equipped-chips as nodes in electronic network. As a result, the circuit and apparatus disclosed in present invention can improve electronic system's performance from the time synchronization perspective.

Abstract: A loss of lock detection circuit includes detection circuitry and pulse accumulation circuitry. The detection circuitry includes a first flip-flop, a second flip-flop, and a third flip-flop. The first flip-flop is configured to synchronize a data stream to a first edge of a clock signal. The second flip-flop is configured to synchronize the data stream to a second edge of the clock signal. The third flip-flop is clocked by the data stream, and is configured to store a combined output of the first flip-flop and the second flip-flop at an edge of the data stream. The pulse accumulation circuitry is coupled to the detection circuitry. The pulse accumulation circuitry is configured to collect pulses generated by the third flip-flop.

Abstract: Systems and methods for distributing in an aircraft are provided. More particularly, in one embodiment, a system can include one or more gas turbine engines configured to provide propulsion and electrical power to an aircraft. The system can further include one or more electrical engines configured to provide propulsion for the aircraft. The system can include one or more first electrical power systems configured to provide power to the one or more electrical engines for one or more electrical power propulsion loads for the aircraft. The system can further include one or more second electrical power systems configured to provide power for one or more non-propulsion electrical power loads of the aircraft.

Abstract: Apparatuses and methods for indirect phase variation detection are disclosed herein. An example apparatus may include a clock generator circuit comprising a delay-locked loop (DLL) circuit configured to adjust a phase of a clock signal based on a phase of a feedback clock signal during an initial phase-lock operation. The DLL circuit includes a phase deviation detection circuit configured to detect a variation in a phase of the clock signal based on variations in gate delays of an oscillation circuit, and to initiate a subsequent phase-lock operation in response to detecting variations in the gate delays of the oscillation circuit.

Abstract: A circuit includes a reference clock terminal configured to receive a signal indicative of a reference clock, multiple low power oscillators (LPOs) and a controller. Each LPO is operable in at least one of three states including a sleep state in which the LPO is powered off, a calibration state in which the LPO undergoes calibration and an active mode in which the LPO is configured to provide a real-time clock based on the reference clock. The controller controls operation of the LPOs such that at most a single LPO is in the active state at any given time.

Abstract: Apparatus and methods for removing leakage from a qubit. In one aspect, an apparatus includes one or more qubits, wherein each qubit facilitates occupation of at least one of a plurality of qubit levels, the qubit levels including two computational levels and one or more non-computational levels that are each higher than the computational levels, wherein the qubit facilitates transitions between qubit levels associated with a corresponding transition frequency; a cavity, wherein the cavity defines a cavity frequency; one or more couplers coupling each qubit to the cavity; one or more couplers coupling the cavity to an environment external to the one or more qubits and the cavity; a frequency controller that controls the frequency of each qubit such that, for each qubit, the frequency of the qubit is adjusted relative to the cavity frequency such that a population of a non-computational level is transferred to the cavity.

Abstract: A system includes an oscillator, a frequency divider, and a delay circuit. The oscillator may generate a clock signal using a reference signal. A frequency of the clock signal may be a non-integer multiple of a frequency of the reference signal. The frequency divider may generate a feedback signal using the clock signal and an adjustment factor based on the non-integer multiple. The delay circuit may select a particular delayed feedback signal from a plurality of delayed feedback signals based on a value of the adjustment factor. Each of the delayed feedback signals may be generated using periods of the clock signal. The delay circuit may also modify the particular delayed feedback signal using a portion of a period of the clock signal based on the adjustment factor. The oscillator may also adjust the frequency of the clock signal using the reference signal and the particular delayed feedback signal.

Abstract: Low power solutions can be provided in a serial bus system with a logic controller circuit. The logic controller circuit can include analog circuitry that includes a plurality of analog components and trimming circuitry for configuring the analog components. Digital circuitry can be configured to switch between an active mode and a hibernation mode, wherein the hibernation mode consumes less current than the active mode. A voltage regulator circuit can be configured to generate a regulated voltage from a supply voltage. A reset generation circuit can be configured to determine that the supply voltage has reached a first threshold voltage level and enable the voltage regulator circuit. When the regulated voltage has reached a second threshold voltage level and the supply voltage has reached a third threshold voltage level, the digital circuitry can be switched to the active mode.

Abstract: A duty cycle correction (DCC) circuit includes first and second pluralities of logic gates, a low pass filter, an error amplifier, and a differential amplifier. The DCC circuit receives first and second clock signals from the VCO. The first and second pluralities of logic gates receive first and second superimposed clock signals and generate first and second output clock signals, respectively. The error amplifier rectifies a common error of the first and second output clock signals, and generates a common mode error voltage signal. The differential amplifier generates first and second error signals based on the common mode error voltage signal. The first and second error signals converge the duty cycles of the first and second output clock signals to a 50% duty cycle.

Abstract: A system for assigning a characterization and calibrating a parameter is disclosed. The system includes a frequency measurement circuit and a finite state machine. The frequency measurement circuit is configured to measure frequencies of an oscillatory signal and to generate a measurement signal including measured frequencies. The finite state machine is configured to control measurements by the frequency measurement circuit, to assign a characterization to a parameter based on the measurement signal, and to generate a calibration signal based on the characterized parameter.

Abstract: Various embodiments of the present disclosure provide system for optimizing electricity generation in a vehicle by managing temperature in vehicle engine and various components to increase efficiency of the engine and various components. In one embodiment, the electricity management system includes a generator connected to a high-power storage device, such as a battery or a capacitor, and a DC-DC converter which includes multiple voltage set-points.

Abstract: A power converter system converts power from an input source for delivery to an active load. An input current surge at startup may be reduced by combining power converter switch resistance modulation with active load control. In another aspect, an input current surge at startup in an array of power converters may be reduced by periodically reconfiguring the array during the startup phase to accumulatively increase the output voltage up to a predetermined output voltage. A power converter may include a controller that provides an over-current signal to the load to reduce the load or advise of potential voltage perturbations.

Abstract: A pulse width modulation (PWM) control method for a five-level inverting circuit is provided. The five-level inverting circuit includes a first capacitor, a second capacitor, a third capacitor and first to eighth switch branches. In this PWM control method, the control logic is set to enable the first and fourth switch branches to be turned on in a complementary manner, the second and fifth switch branches to be turned on in a complementary manner, the third and sixth switch branches to be turned on in a complementary manner, and the seventh and eighth switch branches to be turned on in a complementary manner, and enable the first and second switch branches to be turned on in an interlocking manner, and the sixth and fifth switch branches to be turned on in an interlocking manner.

Abstract: The disclosure provides a phase locked loop, PLL, for phase locking an output signal to a reference signal. The PLL comprises a reference path providing the reference signal to a first input of a phase detector, a feedback loop providing the output signal of the PLL as a feedback signal to a second input of the phase detector, a controllable oscillator generating the output signal based on at least a phase difference between reference and feedback signal, a digital-to-time converter, DTC, delaying a signal that is provided at one of the first and second input, a delay calculation path for calculating a DTC delay value. The PLL further comprises a randomization unit for generating and adding a random offset, i.e. a pseudo-random integer, to the delay value. The offset is such that a target output of the phase detector remains substantially unchanged.

Abstract: A phase locked loop is disclosed comprising: a phase detector, a loop filter, a frequency controller oscillator and a lock detector. The phase detector is operable in a bang-bang mode to provide a binary phase error signal indicating whether there is a positive or negative phase difference between a reference signal and a feedback signal. The loop filter is configured to provide a control signal derived from the binary phase error signal. The frequency controlled oscillator is configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal. The lock/unlock detector is configured to determine a lock/unlock state of the phase locked loop, the lock/unlock state derived from a duty cycle and/or spectral content of the binary phase error signal.

Abstract: In a general aspect, an apparatus can include a low-side drive circuit configured to control a low-side device of a power semiconductor device pair and a high-side drive circuit configured to control a high-side device of the power semiconductor device pair. The high-side drive circuit can include an input circuit configured to receive an input signal and produce, based on the input signal, a first control signal, from which a latch set signal is produced to turn on the high-side device, and a second control signal, from which a latch reset signal is produced to turn off the high-side device. The high-side drive circuit can further include an overlap-prevention circuit configured to prevent timing overlap between the second control signal and a voltage-recovery period of the high-voltage circuit, where the voltage-recovery period occurs after turning off the high-side device of the power semiconductor device pair.

Abstract: Embodiments of the present disclosure describe techniques for reducing human exposure to wireless energy in wireless power delivery environments. In some embodiments, a wireless power reception apparatus configured to receive wireless power from a wireless charging system in a wireless power delivery environment is disclosed. The wireless power reception apparatus includes a control system and an antenna array. In some embodiments, the control system is configured to dynamically adjust transmission and reception radiation patterns of the antenna array to reduce human exposure to wireless radio frequency (RF) energy.

Abstract: Disclosed herein are systems and methods for electrically coupling energy storage devices to an external load or power source. Examples of such coupling include connecting energy storage devices to an electric power grid using a power conversion system with suitable characteristics including, for example, active/real power and reactive power control capabilities, response time, current, voltage, phase, frequency, fault protection and/or information exchange protocols. The power conversion system can include an inverter.

Abstract: Systems and methods for power distribution allocation are provided. A system may establish a first wireless connection between the system and a first mobile device. The system may receive a first power request from the first mobile device, the first power request associated with a first minimum energy charge of the first mobile device, and may determine an available charging capacity of the charging system. The system may determine a first energy charge to provide wirelessly to the first mobile device, and may establish a second wireless connection with a second mobile device. The system may receive a second power request from the second mobile device, and may receive a first charge indicator from the first mobile device associated with a present charging status of the first mobile device. The system may determine a second energy charge to provide wirelessly to the second mobile device.