Abstract: The invention concerns a driver circuit for driving a P-Channel MOSFET. The driver circuit is fed by a DC voltage supplied at a power input and it receives a control signal at a control input. The control signal includes the information for controlling a switching of a P-Channel MOSFET the gate of which is connected to a drive output of the driver circuit. For generating the drive signal the driver circuit includes a turn-off bipolar transistor which is powered by the supply voltage received at the power input in that its collector is connected to the power input. The control signal received at the control input is amplified by means of a current amplifier and fed to the base of the bipolar transistor via an inverting capacitor. In response to the amplified control signal at its base, the bipolar transistor actively generates a turn-off signal and provides the turn-off signal to the drive output in that the emitter of the bipolar transistor is connected to the drive output.

Abstract: An electronic device and method of determining an abnormality or a normality of a connecting unit in an electronic device is provided. The electronic device includes an external device connecting unit having a first function connecting unit and a second function connecting unit, wherein the first function connecting unit includes a first identification (first ID) pin configured to detect a connection with an external electronic device, and wherein the second function connecting unit includes a second identification (second ID) pin configured to detect the connection with the external electronic device, and a processor configured to determine that an abnormality occurs in the external device connecting unit when values measured from the first ID pin and the second ID pin satisfy a predetermined condition.

Abstract: A bootstrapped sampling switch may be used at lower supply voltages due to its high linearity, wherein the sampled voltage may be substantially higher than the supply voltage. A 2.7 volt or lower DC supply may be used with this sampling switch to sample a much higher voltage. A plurality of these high voltage transmission gate switches may be connected directly together, thereby removing a primary source of channel-to-channel mismatch (the active buffer/voltage reduction circuit) and enables new methods of error compensation not previously possible. The sampling switch circuit does not consume DC current from what is being measured. There may be a small switched capacitor voltage charge and there may be some voltage leakage, but no DC current is drawn from the voltage input being measured.

Abstract: Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.

Abstract: A level shift circuit is provided, which includes a boost circuit and a voltage converting circuit. The boost circuit is coupled to a first high voltage terminal to receive an input voltage signal. The boost circuit includes at least one low threshold voltage element and is configured to boost the input voltage signal. The voltage converting circuit is coupled to a second high-voltage terminal and includes a low-pass filter circuit, a high-pass filter circuit, an upper switch element and a lower switch element. The upper switch element and the lower switch element are electrically cascaded between the second high-voltage terminal and a low voltage terminal. The low-pass filter circuit and the high-pass filter are electrically connected between the control terminal of the upper switch element and the control terminal of the lower switch element. The upper switch element and the lower switch element are standard threshold voltage elements.

Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.

Abstract: A push-pull tunable coupler includes a push transformer, a pull transformer and two compound Josephson junctions arranged in upper and lower branches. Absent biasing, the balanced push and pull of current between the branches causes current from a first object to circulate within a loop and not to be coupled to a second object. Biasing of at least one of the compound Josephson junctions unbalances the push and pull of current in the branches to couple the first and second objects. The coupler has reduced sensitivity to differential-mode noise around the off state, is completely insensitive to common-mode noise, and is capable of inverting the coupled signal with appropriate relative biasing of the compound Josephson junctions.

Abstract: A skew control loop circuit for controlling a skew between a plurality of digital signals, and a semiconductor device, and a method of operation, for the same, may be provided. The skew control loop circuit comprises a skew detector for detecting a phase difference between the digital signals, a skew control circuit adapted for controlling an operation of the skew control loop circuit. The skew control circuit is operable in a first operating mode and in a second operating mode. The skew control loop circuit comprises also an enable input of the skew detector, wherein the enable input is adapted for receiving an enable input signal, generated by the skew control circuit, wherein the enable input is adapted for selectively enable or disable a phase detection operation of the skew detector, and wherein the enable input signal is only active during the first operating mode.

Abstract: A frequency generating circuit includes: a delay circuit, arranged to operably delay an output frequency signal to generate a delayed signal; a quartz crystal resonator, coupled with the delay circuit, arranged to operably conduct a band-pass filtering operation on the delayed signal to generate the output frequency signal; and a delay control circuit, coupled with the delay circuit, arranged to operably control a phase delay amount of the delay circuit to thereby control the phase of the delayed signal.

Abstract: A power transmitter transfers power to a power receiver using a wireless power signal. The power transmitter comprises an inductor driven by a power signal generator to provide the power signal. A calibration controller determines whether a power loss calibration has been performed for the power transmitter and power receiver pairing. The calibration adapts an expected relationship between a received power indication provided by the power receiver and a transmitted power indication for the power transmitter. A power limiter restricts the power provided to the inductor to not exceed a threshold unless a power loss calibration has been performed for the pairing. The expected relationship may be used to detect unaccounted for power losses, e.g. due to foreign objects being present. The calibrated expected relationship may provide improved accuracy allowing accurate detection at higher power levels. At lower power levels such accuracy is not needed, and no calibration needs to be performed.

Abstract: Systems and methods for controlling power distribution are provided. The method includes receiving a power command, wherein the power command requests a discharge from one or more BESS units, and wherein the one or more BESS units are housed in one or more temperature controlled rooms. For each of the one or more temperature controlled rooms, a lowest energy remaining of the one or more BESS units in the temperature controlled room is determined; a low threshold is determined based on the determined lowest energy remaining and a floor; a limit is determined based on the determined low threshold; and the limit is assigned to each of the one or more BESS units housed in the temperature controlled room. The method includes causing the power command to be at least partially satisfied by the one or more BESS units based on the assigned limits.

Abstract: A system that can include a detector that can monitor a voltage at an input of a transistor device over a period of time and provide a signal having a value representative of a capacitance between the input and an output of the transistor device. The system can further include a driver that can have a programmable drive strength and be coupled to input of the transistor device to drive the transistor device at the input thereof. The system can further include a controller that can configure the driver based on the signal to drive the transistor device with a corresponding drive strength.

Abstract: A bidirectional power converter circuit is controlled via a hysteresis loop such that the bidirectional power converter circuit can compensate in near real time for variations and even changes in transmit and receive coil locations without damaging components of the system. Because the bidirectional power converter is capable of both transmitting and receiving power (at different times), one circuit and board may be used as the main component in multiple wireless power converter designs.

Abstract: A frequency divider includes first circuitry, second circuitry, and third circuitry. The first circuitry includes divide-by-two (div2) frequency divider circuitry, and the second circuitry includes additional circuitry for a divide-by-three (div3) frequency divider. The second circuitry is selectively enabled using a control signal and can receive signals from the first circuitry when enabled. Specifically, the second circuitry is enabled in the div3 mode but is not enabled in the div2 mode. The third circuitry receives signals from the first circuitry and also receives signals from the second circuitry when the second circuitry is enabled. The first circuitry and the third circuitry function as a div2 frequency divider when the second circuitry is not enabled. The first circuitry, the second circuitry, and the third circuitry function as a div3 frequency divider when the second circuitry is enabled.

Abstract: Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second and third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.

Abstract: Techniques for wireless transmitting power are described. An example power transmitting unit includes a magnetic resonance-type transmit coil array comprising a plurality of coil elements, wherein each coil element is tuned to a same resonant frequency. The power transmitting unit also includes a power generating circuitry to deliver current to the transmit coil array to wirelessly power a device within an active wireless charging area of at least one of the plurality of coil elements. Each coil element exhibits a plurality of zero point distances and the spacing between neighboring coil elements corresponds with the plurality of zero point distances.

Abstract: A power transmission device includes an inverter using a frequency f11 lower than a frequency f0 between a first resonator and a second resonator or a frequency f12 higher than the frequency f0 to generate a first power; an oscillator using a frequency f10 lower than a frequency fr between the first resonator and the second resonator or a frequency f20 higher than the frequency fr to generate a second power; and a power transmission control circuitry setting a foreign object detection period between first and second transmission periods, using the frequency f11 or frequency f12 in the first transmission period, using the frequency f10 or frequency f20 in the foreign object detection period, and if it is determined that a substance is present in the foreign object detection period, transmitting power in the second transmission period at a frequency different from the frequency used in the first transmission period.

Abstract: In one example, a circuit includes a voltage source, an inductive load, a capacitor, a switching unit, and a load unit. The switching unit is configured to operate in a first state and a second state. The switching unit couples the inductive load to the voltage source during the first state. The switching unit couples the inductive load to the capacitor during the second state. The load unit is configured to receive energy from the capacitor based on a comparison of a voltage of the capacitor and a reference voltage.

Abstract: A vehicle system includes multiple DC-DC converter circuits, vehicle batteries, and vehicle power distribution buses. Each vehicle battery is electrically connected in parallel to each of the DC-DC converter circuits. Each of the vehicle batteries is also electrically connected in parallel to one another. Further, each of the DC-DC converter circuits and each of the vehicle batteries are electrically connected to multiple vehicle power distribution buses.

Abstract: To speed up output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure the output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, a group of the output pulses is advanced during the alignment procedure to reduce the spacing between them. After determining the delay value averaged over the group of output pulses subsequent output pulses are restored to their normal spacing and time locations.