Patents Examined by Adam Houston
  • Patent number: 10067203
    Abstract: The present disclosure relates possible implementations for utilizing energy storage elements in conjunction with a MRI system. Similarly, various associated control mechanisms are discussed. In certain embodiments, one or both of peak power shaving or energy backup may be facilitated by use of the energy storage elements. Certain such implementations may facilitate the use of higher-power MRI systems with an existing electrical infrastructure.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: September 4, 2018
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Jayanti Ganesh, Juan Antonio Sabate, Rajendra Naik, Margaret Ann Wiza, Viswanathan Kanakasabai, Michael Thomas Rose
  • Patent number: 10063081
    Abstract: An energy harvesting direct current to direct current ‘DC-to-DC’ converter circuit is presented. It is comprised of an energy storage element, an input configured to receive an input voltage, an output; switching means configured to perform cycles. Each cycle is marked when the input voltage reaches a reference voltage, switching the circuit such that the energy storage element enters into an energy charging state in which the energy storage element stores energy provided by the input voltage. Control means is configured to determine the reference voltage based on the number of cycles per time period performed by the circuit.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: August 28, 2018
    Inventor: Marinus Wilhelmus Kruiskamp
  • Patent number: 10063244
    Abstract: Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: August 28, 2018
    Assignee: SiTime Corporation
    Inventor: Michael H. Perrott
  • Patent number: 10063247
    Abstract: A phase-locked loop (PLL) has at least two parallel loops. The loops share an oscillator, a counter connected with the oscillator, a multiplexer, and a loop filter. Each loop has a register sampling the oscillator phase from the counter, and a phase predictor which uses a fractional-N frequency control word (FCW) to calculate a predicted phase as an integer number. The loop forwards the integer difference between the sampled phase and the predicted phase to the multiplexer, which selects one of the loops and provides the difference to the loop filter. Loops that are not selected use a monitor-and-adjust function to keep the difference in track with the difference of a selected loop. Loops may provide a loop sleep function and the PLL may also provide an oscillator sleep function.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: August 28, 2018
    Assignee: Perceptia Devices, Inc.
    Inventors: Julian Jenkins, André Henri Grouwstra
  • Patent number: 10063246
    Abstract: A phase-locked loop (PLL) has an oscillator, a counter and a register to sample the oscillator phase as an integer number. A phase predictor uses a fractional-N frequency control word (FCW) to calculate a predicted phase as an integer number. The integer difference between the sampled phase and the predicted phase is used as loop filter input, to generate an oscillator control code that adjusts the oscillator frequency. The phase predictor may provide noise shaping, for example via a MASH modulator. The PLL may be implemented with dedicated or off-the-shelf circuitry, in an FPGA, or with a programmable processor. A tangible non-transitory memory may hold an associated software instructions for fractional-N phase locking.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: August 28, 2018
    Assignee: Perceptia Devices, Inc.
    Inventors: André Grouwstra, Julian Jenkins
  • Patent number: 10063111
    Abstract: The disclosure relates to systems and methods for managing wireless power transfer network for communication devices, providing central management in communication with a cloud based network for enabling remote activation. The system comprising at least one wireless power outlet and at least one management server. The management system, of the current disclosure, is enabling possible remote activation and associate between a communication device and a wireless power receiver, thus, allowing power transfer between the remote health check and maintenance of all of wireless power outlets from an outlet to a communication device via an associated wireless power receiver as well as providing communication based upon its UDID associated with the relevant RXID.
    Type: Grant
    Filed: January 1, 2015
    Date of Patent: August 28, 2018
    Assignee: POWERMAT TECHNOLOGIES LTD.
    Inventors: Eduardo Alperin, Aya Kantor, Ian Podkamien
  • Patent number: 10063230
    Abstract: An electronic switch with force feedback function includes a base, an actuating component and a. The actuating component is movably connected to the base, and includes a. The magnetic field generating module is disposed on the base, and provides a magnetic repulsive force to the magnetic unit for force feedback while the actuating component moves close to the base.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: August 28, 2018
    Assignee: PixArt Imaging Inc.
    Inventors: Tsung-Fa Wang, Shih-Wei Kuo
  • Patent number: 10056912
    Abstract: A circuit for phase locked loop (PLL) multiple spur cancellation includes multiple spur cancellation circuits and a number of multiplexers that are coupled to respective input ports of the spur cancellation circuits. The circuit further includes a number of demultiplexers that are coupled to respective output ports of the spur cancellation circuits. Each spur cancellation circuit can cancel a spur associated with a spur source, and input nodes of the multiplexers and output nodes of the demultiplexers are coupled to different connection points of a PLL circuit.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: August 21, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Long Bu, David Christopher Garrett, Dandan Li
  • Patent number: 10050449
    Abstract: A wireless rail system for providing power and control to auxiliary devices on the rail is disclosed. Such a system includes a one or more channels mounted to a structural building component forming a rail. Auxiliary devices on the rail communicate with each other and user devices. Each of the auxiliary devices are addressable either wirelessly or by a parallel bus within the rail. The auxiliary devices are connected and disconnected from the rail by rotating approximately 90 degrees.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: August 14, 2018
    Assignee: Hall Labs, LLC
    Inventors: David R. Hall, Jerome Miles
  • Patent number: 10050634
    Abstract: A system includes an oscillator, a frequency divider, and a delay circuit. The oscillator may generate a clock signal using a reference signal. A frequency of the clock signal may be a non-integer multiple of a frequency of the reference signal. The frequency divider may generate a feedback signal using the clock signal and an adjustment factor based on the non-integer multiple. The delay circuit may select a particular delayed feedback signal from a plurality of delayed feedback signals based on a value of the adjustment factor. Each of the delayed feedback signals may be generated using periods of the clock signal. The delay circuit may also modify the particular delayed feedback signal using a portion of a period of the clock signal based on the adjustment factor. The oscillator may also adjust the frequency of the clock signal using the reference signal and the particular delayed feedback signal.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: August 14, 2018
    Assignee: Apple Inc.
    Inventors: Feng Zhao, Wei Deng, Dennis M. Fischette, Jr.
  • Patent number: 10044357
    Abstract: A clock recovery device is provided. The clock recovery device includes a clock data recovery circuit and a fast relock circuit. The clock data recovery circuit is configured to generate an output clock signal in response to an input clock signal. The clock data recovery circuit includes a charge pump for generating a control voltage and a voltage controlled block for generating the output clock signal based on the control voltage. The fast relock circuit is configured to convert a comparison signal indicating a comparison result between the input clock signal and the output clock signal to an analog output voltage. When the charge pump is disabled, an output path of the fast relock circuit is turned on, and the analog output voltage is applied to an input of the voltage controlled block.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: August 7, 2018
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Wei-Sheng Tseng, Chih-Lu Wei
  • Patent number: 10038336
    Abstract: The present invention relates to a power duplication apparatus for an HVDC system and a control method therefor, and the power duplication apparatus for an HVDC system comprises: a first independent power generator receiving first input power so as to generate and output first power; a second independent power generator receiving second input power so as to generate and output the first power; a first power supplier selectively receiving the first power output, respectively, from the first independent power generator and the second independent power generator so as to convert the first power into second power having a smaller size than that of the first power and output the same; a second power supplier for selectively receiving the first power output, respectively, from the first independent power generator and the second independent power generator so as to convert the first power into the second power having a smaller size than that of the first power and output the same; a first HVDC controller for receiv
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: July 31, 2018
    Assignee: HYOSUNG CORPORATION
    Inventors: Jae-Hoon Oh, Hyo-Jin Kang
  • Patent number: 10033190
    Abstract: The disclosure relates to an inverter with at least two DC inputs, which are coupled to a common DC link, which is connected to an inverter bridge. At least one of the DC inputs is coupled to an additional DC link. The disclosure also relates to a PV system comprising such an inverter and to a method for controlling such an inverter of a PV system, wherein a power flow from at least one of the DC inputs is directed into the common DC link and/or into the additional DC link on the basis of suitably coordinated control of the DC-DC converter and of an additional DC-DC converter allocated to the additional DC link.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: July 24, 2018
    Assignee: SMA Solar Technology AG
    Inventors: Carsten Ewig, Dietmar Meerwart
  • Patent number: 10027179
    Abstract: A system and method for continuous wireless monitoring and powering of at least one sensor is presented. The system is generally comprised of at least one sensor, at least one RF transmitter, an energy harvester, an energy storage unit, a microprocessor and a receiving antenna. Multiple RF transmitters may be positioned in an orthogonal orientation within reach of the receiving antennae to provide equally strong RF fields. The system may additionally include metal shielding around the area in which the system is operating.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: July 17, 2018
    Assignee: University of South Florida
    Inventors: Simon Antonio Bello, Christopher L. Passaglia
  • Patent number: 10027178
    Abstract: A wireless power transmitting and receiving device includes: a coil including a first section having a first number of turns and configured to receive power and a second section having a second number of turns different from the first number of turns and configured to transmit power and a converting and rectifying unit configured to: rectify the power received through the coil, convert externally-supplied power into alternating current power, and apply the alternating current power to the coil.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: July 17, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Sang Ho Cho
  • Patent number: 10028349
    Abstract: A Light Emitting Diode (LED) light includes a bridge rectifier configured to be powered by an alternating current power source and to produce a rectified output. Control circuitry couples to the bridge rectifier and is configured to produce a shunt signal when the rectified output is less than a threshold voltage. A series connected Light Emitting Diode (LED) string includes a first group of LEDs and a second group of LEDs. A switch couples to a first side of the second group of LEDs and is controlled by the shunt signal to deactivate the second group of LEDs. The control circuitry may include a ratio metric series resistor string configured to sense a proportion of the rectified output and an inverter configured to generate the shunt signal based on the proportion of the rectified output.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: July 17, 2018
    Assignee: Austin IP Partners
    Inventors: Mathew A. Rybicki, Daniel Patrick Mulligan
  • Patent number: 10027187
    Abstract: An energy distribution system is provided with a plurality of energy harvesting devices and a plurality of power draining devices in a wireless mesh energy network. One or more of the energy harvesting devices wirelessly transmits electrical energy to one or more of the power draining devices to power the power draining devices. The energy harvesting devices have harvesting mechanisms that harness and converts kinetic energy of motion, mechanical energy or other forms of energy from other sources into electrical energy. The power draining devices are configured to communicate a signal requesting for power and power data to the energy harvesting devices. The energy harvesting devices utilize the power data to prioritize which power draining devices will wirelessly receive electrical energy. This system would decrease or eliminate the need for attachment to the energy grid.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: July 17, 2018
    Assignee: Uncharted Power, Inc.
    Inventor: Jessica Osemudiamen Idoni Matthews
  • Patent number: 10020676
    Abstract: One example discloses a watchdog circuit: wherein the watchdog circuit is configured to receive a primary ground from a primary power supply, and a backup ground from a backup power supply; wherein the watchdog circuit includes a ground switch coupled to the primary ground and the backup ground; and wherein the ground switch is configured to isolate the primary ground from the backup ground in response to a fault signal.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: July 10, 2018
    Assignee: NXP B.V.
    Inventors: Ge Wang, Harold Garth Hanson
  • Patent number: 10020813
    Abstract: A clocking system disclosed herein includes a delay locked loop (DLL) circuit with a plurality of delay elements, where the DLL circuit is configured to receive a clock input signal and generate a plurality of clock output signals. The clocking system also includes a feed-forward system configured to increase the speed of the clock signal transmission through the delay elements and to enforce symmetric zero crossings of the clock signal at each of the plurality of delay elements.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: July 10, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Richard McCauley, Barry Thompson, Stefan Wurster
  • Patent number: 10009036
    Abstract: An apparatus and a method. The apparatus includes a counter array; a ring oscillator that is electrically coupled to the counter array, where the counter array counts a number of cycles in the ring oscillator; an analog-to-digital converter (ADC) driver that is electrically coupled to the ring oscillator; and an ADC that is electrically coupled to the ADC driver, where an output of the ADC is electrically coupled to the ring oscillator.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: June 26, 2018
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Wing-Fai Loke, Chih-Wei Yao