Abstract: The present disclosure described herein relates to wireless power transfer systems and methods that efficiently and safely transfer power to electronic devices. In an aspect of the disclosure, a method for wirelessly transmitting power is provided. The method includes during a first time period, transmitting power at a first power level from a wireless power transmitter to the wireless power receiver. The method further includes determining a frequency for transmitting power at a second power level based on a ratio of a current level of the wireless power receiver to a current level of a wireless power transmitter at the first power level. The method further includes during a second time period, transmitting power at the second power level and at the frequency, the first power level lower than the second power level.

Abstract: Provided are a driver circuit which suppresses damage of a semiconductor element due to ESD in a manufacturing process, a method of manufacturing the driver circuit. Further provided are a driver circuit provided with a protection circuit with low leakage current, and a method of manufacturing the driver circuit. By providing a protection circuit in a driver circuit to be electrically connected to a semiconductor element in the driver circuit, and by forming, at the same time, a transistor which serves as the semiconductor element in the driver circuit and a transistor included in the protection circuit in the driver circuit, damage of the semiconductor element due to ESD is suppressed in the process of manufacturing the driver circuit. Further, by using an oxide semiconductor film for the transistor included in the protection circuit in the driver circuit, leakage current in the protection circuit is reduced.

Abstract: A power supplying method is adapted to supply power to any one of external electronic devices with voltage-stabilized capacitors of different specifications. The power supplying method includes: generating a periodic signal; periodically turning on and off a load-switch circuit by the periodic signal to enable the load-switch circuit to periodically charge and discharge the voltage-stabilized capacitor; generating an enable signal following the periodic signal; continuously turning on the load-switch circuit by the enable signal to enable the load-switch circuit to supply the power to the external electronic device according to a flag signal; and detecting the amount of a current supplied to the external electronic device by the load-switch circuit to determine a level of the flag signal. During periodically charging and discharging the voltage-stabilized capacitor, the amount of the current supplied to the external electronic device is gradually decreased.

Abstract: A switch drive circuit includes a high-side power supply section, a latch circuit, a high-side driver, a low-side driver, and a high-side switch control circuit. The latch circuit latches a logical level of a high-side switching signal at the time of performing switching of a high-side switch. The high-side driver drives the high-side switch by the high-side switching signal outputted from the latch circuit. The low-side driver drives a low-side switch by a low-side switching signal. The high-side switch control circuit sets, at the time of stopping the switching of the high-side switch, a stop established state in which the logical level of the high-side switching signal is fixed at a stop logic level, and releases the stop established state at the time of performing the switching of the high-side switch.

Abstract: A magnitude difference between intrinsic positive and negative current components forming a PLL's charge pump output current is determined by simultaneously outputting the intrinsic positive and negative pump current components, and incrementally increasing a bias current added to one of the intrinsic current components (e.g., such that the total positive current component is gradually increased). Calibration control voltages generated by the calibration pump output current are measured to determine when magnitudes of the adjusted (e.g., positive) current component and the non-adjusted/intrinsic (e.g., negative) current component are equal, and the bias current amount required to achieve equalization is stored as a digital converter code. During subsequent normal PLL operations, the digital converter code is utilized to control the charge pump such that the magnitude of the positive current component is adjusted by the bias current amount such that the positive and negative current components are matched.

Abstract: A phase-locked loop (PLL) has a primary loop (with a reference clock) and a secondary loop (with a stable reference clock). The secondary loop may include a fractional-N PLL, and may include a secondary loop filter, oscillator, output clock counter, and phase predictor using a rational secondary frequency control word (FCW). The primary loop has a register sampling the oscillator phase from the counter, and a phase predictor which uses a primary fractional-N FCW to calculate a predicted phase as an integer number. The primary loop forwards the integer difference between the sampled phase and the predicted phase to a primary loop filter, which outputs the secondary FCW. The primary loop filter has a much lower bandwidth than the secondary loop filter. The PLL may have multiple primary loops, with a hitless switching function. A primary loop may have sleep mode. The PLL may also provide an oscillator sleep function.

Abstract: A circuit for measuring clock jitter includes: an internal signal generator configured to generate an internal clock signal and a single pulse signal, respectively synchronized with an input clock signal; a plurality of delay units being connected in series with each other and configured to generate respective delayed clock signals; a plurality of latch circuits configured to latch the single pulse signal in synchronization with the respective delayed clock signals, and output sampling signals; and a count sub-circuit configured to output a count value resulting from counting a number of active sampling signals of the sampling signals.

Abstract: An output circuit has: a first driver circuit configured to receive a voltage of an input terminal and output a first voltage to an output terminal; a first comparison circuit configured to compare a first reference voltage with a voltage of the output terminal; a second driver circuit configured to receive the voltage of the input terminal and output a second voltage to the output terminal and become an off state according to a comparison result of the first comparison circuit; a second comparison circuit configured to compare a second reference voltage different from the first reference voltage with the voltage of the output terminal; and a third driver circuit configured to receive the voltage of the input terminal and output a third voltage to the output terminal and become an off state according to a comparison result of the second comparison circuit.

Abstract: Wireless charging, such as that conducted according to standards formed by the AirFuel Alliance and/or various other industry standards for wireless charging, can cause interference with data transfer on a cellular modem of a mobile device. Systems, devices, and methods herein provide power breaks where a power transmitter unit (PTU) will stop generating an electromagnetic field used to charge a power receiver unit (PRU). During the power break, the mobile device can send or receive data over the cellular modem with less or no interference from the wireless charging operations. If the PTU cannot provide a power break, the PRU de-tunes a receive resonator circuit in the PRU to mitigate the interference from the wireless charging operations. Further, the power breaks can also be used by PTUs to scan for near field communication (NFC) tags or devices that could be damaged by wireless charging activities.

Abstract: A wireless power transmitter according to one exemplary embodiment of the present disclosure includes a body having a transmitting coil unit embedded therein, and having one surface with a portable electronic device located thereon, the portable electronic device receiving power from the transmitting coil unit in a wireless manner, and a driving unit that is configured to rotate the transmitting coil unit centering on a shaft penetrating through the transmitting coil unit, such that the transmitting coil unit is moved close to a receiving coil unit of the portable electronic device.

Abstract: A digital PLL is disclosed. In one embodiment, the digital PLL includes a TDC coupled to receive a reference clock signal and feedback signal. The TDC includes a chain of serially-coupled delay elements. An oscillator in the PLL is configured to generate a periodic output signal. A divider is coupled to receive the periodic output signal and generate the feedback signal provided to the TDC. The digital PLL also includes a control circuit. During a phase-locking procedure, each of the serially-coupled delay elements is enabled for fast phase capture. However, once phase-lock has been detected by observing TDC output code, the control circuit is adaptively configured to disable all but a subset of the delay elements for saving power.

Abstract: A system for wireless power transmission is provided. The system comprises a plurality of tiles configured to operate as one functional unit. At least one of the tiles comprises an antenna and a radio frequency integrated circuit (RFIC) coupled to the antenna and the RFIC is configured to engage the antenna such that the antenna emits a plurality of wireless power waves defining a pocket of energy.

Abstract: Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Abstract: The phase-locked loop circuit according to one embodiment includes a low-pass filter including a first transistor, and a second transistor. The low-pass filter converts a first current into a first voltage, and a second current into a second voltage. The first current and the second current are generated in accordance with a pulse width of the same signal. The first transistor includes a gate input with the first voltage, a first terminal grounded, a second terminal electrically coupled to a gate of the second transistor, and a gate oxide film thicker than that of the second transistor. The second transistor includes the gate input with the second voltage.

Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.

Abstract: An apparatus includes a signal generator. The signal generator includes a voltage controlled oscillator (VCO) coupled to provide an output signal having a frequency. The signal generator further includes an asymmetric divider coupled to receive the output signal of the VCO and to provide an output signal. The output signal of the asymmetric divider has a frequency that is half the frequency of the output signal of the VCO. The asymmetric divider presents a balanced load to the VCO.

Abstract: An apparatus for wireless power transmission is provided. The apparatus comprises a transmitter comprising a first antenna element and a second antenna element. The transmitter is configured to emit a first signal by the first antenna element and a second signal by the second antenna element. The first signal comprises a plurality of wireless power waves establishing a pocket of energy. The second signal is different from the first signal. The second signal provides Wi-Fi access.

Abstract: A load controller is connected with a residential electric load to regulate electric power drawn by the load from a residential a.c. electric power distribution system via power input terminals of the load. A voltmeter is connected to measure voltage at the power input terminals, and an ammeter is connected to measure electric current at the power input terminals. A microprocessor or microcontroller is programmed to compute a source impedance of the power distribution system as seen from the power input terminals using measured voltage and electric current at the power input terminals. The source impedance may be computed by determining an equivalent source voltage as equal to measured voltage at the power input terminals when the electric current at the power input terminals is zero, and computing the source impedance from measured non-zero electric current at the power input terminals in combination with at least the equivalent source voltage.

Abstract: A power distribution system is described. The system includes a main ac busbar and an emergency ac busbar. A hybrid drive system includes an induction electrical machine and a prime mover, the rotor of the electrical machine and the driving end of the prime mover being mechanically coupled to a load by means of a mechanical linkage such as a gearbox. The system includes a first active rectifier/inverter having ac input terminals electrically connected to the main ac busbar, and dc output terminals. The system includes a second active rectifier/inverter having dc input terminals electrically connected to the dc output of the first active rectifier/inverter by a dc link, and ac output terminals electrically connected to the induction electrical machine. A blackout restart system includes a rectifier having ac input terminals selectively electrically connectable to the emergency ac busbar and dc output terminals selectively electrically connectable to the dc link.

Abstract: A hybrid switch apparatus includes a gate drive circuit producing a gate drive signal, a GaN high electron mobility transistor (HEMT) having a first gate, a first drain, and a first source. A silicon (Si) MOSFET has a second gate, a second drain, and a second source. The GaN HEMT and the Si MOSFET are connected in a parallel arrangement so that (i) the first drain and the second drain are electrically connected and (ii) the first source and the second source are electrically connected. The second gate is connected to the gate drive circuit output to receive the gate drive signal. A delay block has an input connected to the gate drive circuit output and an delay block output is configured to produce a delayed gate drive signal for driving the GaN HEMT.