Patents Examined by Andrew J Cheong
  • Patent number: 11537307
    Abstract: A memory sub-system periodically performs a first wear leveling operation using a direct mapping function on a data management unit of a memory component in the memory sub-system at a first frequency. The memory sub-system further periodically performs a second wear leveling operation using indirect mapping on a group of data management units of the memory component at a second frequency, wherein the second wear leveling operation is performed less frequently than the first wear leveling operation.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: December 27, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Ying Yu Tai, Jiangli Zhu, Ning Chen
  • Patent number: 11513722
    Abstract: A memory system includes a non-volatile memory device and a controller. The non-volatile memory device performs operations in parallel on a plurality of memory blocks. The controller determines, in response to a read request on a plane including a target memory block among the plurality of memory blocks, whether to perform a process for a partial suspension on the operations based on suspension counts of the plurality of memory blocks. The controller controls, when performing a process for the partial suspension, the non-volatile memory device to suspend the operation being performed on the target memory block and to keep performing the operations being performed on other memory blocks among the plurality of memory blocks.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: November 29, 2022
    Assignee: SK hynix Inc.
    Inventor: Su Kyung Kim
  • Patent number: 11513966
    Abstract: An apparatus has processing circuitry, load tracking circuitry and value prediction circuitry. In response to an actual value of first target data becoming available for a value-predicted load operation, it is determined whether the actual value matches the predicted value of the first target data determined by the value prediction circuitry, and whether the tracking information indicates that, for a given younger load operation issued before the actual value of the first target data was available, there is a risk of second target data associated with that given load operation having changed after having been loaded. Independent of whether the addresses of the value-predicted load operation and younger load operation correspond, at least the given load operation is re-processed when the value prediction is correct and the tracking information indicates there is a risk of the second target data having changes after being loaded. This protects against ordering violations.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: November 29, 2022
    Assignee: Arm Limited
    Inventor: . Abhishek Raja
  • Patent number: 11507305
    Abstract: Systems and methods enabling garbage collection operations and normal system operations concurrently. Concurrent operations are performed by configuring a similarity group to permit garbage collection and normal operations. This may include creating a new subgroup in a similarity group for write and deduplication purposes such that an impacted subgroup can be cleaned.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: November 22, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Tipper Truong, Mariah Arevalo, Philip Shilane, Kimberly R. Lu, Joseph S. Brandt, Nicholas A. Noto
  • Patent number: 11507874
    Abstract: A method of sharing address information using quantum states includes storing a number, M, of first qubits in a quantum store at a source node and storing classical information tagged to the M first qubits in a classical store at the source node, where the classical information describes a destination node where the M first qubits share entangled qubits. The M first qubits are measured at the source node and a random number is generated that represents an address of the destination node using the measured M first qubits and the classical information describing the destination node. A packet is sent from the source node that includes the generated random number in a quantum address field and further includes data intended for the destination node in a data field. A number, M, of second qubits is stored in a quantum store at the destination node, wherein each of the M first qubits is entangled with a respective one of the M second qubits.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: November 22, 2022
    Assignee: Qubit Moving and Storage, LLC
    Inventors: Gary Vacon, Kristin A. Rauschenbach
  • Patent number: 11500545
    Abstract: A method includes receiving a humidity level in a tape library and determining whether the humidity level is in a predefined range indicative of safe operation. In response to determining that the humidity level is in the predefined range, the method includes allowing performance of operations on magnetic recording tapes. In response to determining that the humidity level is not in the predefined range, the method includes preventing performance of the operations on magnetic recording tapes. A drive-implemented method includes detecting a humidity level within a housing of a tape drive and determining whether the humidity level is in a predefined range indicative of safe operation.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: November 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Shawn M. Nave, Lee Jesionowski
  • Patent number: 11500549
    Abstract: Secure access to data on a storage system via direct connection to an internal fabric of the storage system may be provided. A storage system interface (SSI) may validate each I/O communication originating on the host system before allowing a corresponding I/O communication to be transmitted on the internal fabric. The validation may include applying predefined rules and/or ensuring that the I/O communication conforms to one or more technologies, e.g., NVMe. The SSI may be configured to encrypt I/O communications originating on a host system and to decrypt I/O communications received from the storage system, for example, in embodiments in which data is encrypted in flight from the host system to physical storage devices, and data may be encrypted at rest in memory of the storage system and/or on physical storage devices.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: November 15, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Ian Wigmore, Alesia A. Tringale, Jason J. Duquette
  • Patent number: 11481153
    Abstract: A data storage device may include a nonvolatile memory device, and a controller configured to increase an assert count, when a malfunction occurs while an operation for a command received from a host device is executed, the assert count representing the number of times the malfunction has occurred, and execute a flash translation layer (FTL) resetting operation in a read-dedicated mode in response to an initialization request from the host device when the assert count is greater than or equal to a reference value.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: October 25, 2022
    Assignee: SK hynix Inc.
    Inventors: Dong Hyun Cho, Yeong Dong Gim, Jee Yul Kim
  • Patent number: 11435956
    Abstract: Embodiments of the present disclosure provide a method, an electronic device, and a computer program product for data compression. The method includes: determining an amount of data to be compressed in a storage system; determining, based on the amount of the data to be compressed, a target compression level for compressing the data to be compressed; and compressing the data to be compressed according to the target compression level. In this way, it is possible to compress data to be compressed using a compression level corresponding to the amount of the data to be compressed, thereby improving the efficiency of data compression in the storage system.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: September 6, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Tao Chen, Geng Han
  • Patent number: 11435954
    Abstract: In a method used for maximizing performance of a storage system, saturation points of the storage system for I/O requests of different types and sizes are identified. Normalized tokens are determined based on the saturation points. Unique numbers of normalized tokens are associated with the I/O requests of different types and sizes. A number of normalized tokens for a queue depth limit of a storage device is determined. From the queue depth limit, normalized tokens are allocated to each node in the storage device. I/O requests are processed according to the allocations of normalized tokens.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: September 6, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Shuyu Lee, Vamsi K. Vankamamidi, Jeffrey L. Grummon
  • Patent number: 11422938
    Abstract: A system includes a multi-core shared memory controller (MSMC). The MSMC includes a snoop filter bank, a cache tag bank, and a memory bank. The cache tag bank is connected to both the snoop filter bank and the memory bank. The MSMC further includes a first coherent slave interface connected to a data path that is connected to the snoop filter bank. The MSMC further includes a second coherent slave interface connected to the data path that is connected to the snoop filter bank. The MSMC further includes an external memory master interface connected to the cache tag bank and the memory bank. The system further includes a first processor package connected to the first coherent slave interface and a second processor package connected to the second coherent slave interface. The system further includes an external memory device connected to the external memory master interface.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: August 23, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Matthew David Pierson, Kai Chirca, Timothy David Anderson
  • Patent number: 11416144
    Abstract: A storage system and related method are for operating solid-state storage memory in a storage system. Zones of solid-state storage memory are provided. Each zone includes a portion of the solid-state storage memory. The zone has a data write requirement for the zone for reliability of data reads. The storage system adjusts power loss protection for at least one zone. The adjusting is based on the data write requirement for the zone and responsive to detecting a power loss.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: August 16, 2022
    Assignee: Pure Storage, Inc.
    Inventors: Andrew R. Bernat, Brandon Davis, Mark L. McAuliffe, Zoltan DeWitt, Benjamin Scholbrock, Phillip Hord, Ronald Karr
  • Patent number: 11416407
    Abstract: Operational information in a storage system is collected regarding storage media storage tiers, devices, drives, tracks on drives, and logical storage layers, to determine an estimated amount of time it will take to write data from cache to the intended drive when a new write operation arrives at the storage system. This information is then used to decide which type of cache is most optimal to store the data for the write operation, based on the estimated amount of time it will take to write data out from the cache. By allocating cache slots from a faster cache to write operations that are expected to quickly be written out to memory, and allocating cache slots from the slower cache to write operations that are expected to take more time to be written out to memory, it is possible to increase the availability of the cache slots in the faster cache.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: August 16, 2022
    Assignee: Dell Products, L.P.
    Inventor: John Creed
  • Patent number: 11392490
    Abstract: Systems and methods for marking similarity groups impacted by a garbage collection operation are disclosed. Similarity groups are used to identify segments associated with objects in a computing system. Using deletion records that identify objects to be deleted, the similarity groups impacted by the deletion records can be identified. The live segments associated with the impacted similarity groups are also identified. This allows segments that are associated with the deleted objects and that are not associated with any live objects to be removed.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: July 19, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Kimberly R. Lu, Joseph S. Brandt, Nicholas A. Noto, Tipper Truong, Mariah Arevalo, Philip Shilane
  • Patent number: 11379117
    Abstract: A storage system and method for using host-assisted variable zone speed grade modes to minimize overprovisioning are provided. In one embodiment, a controller of the storage system is configured to receive a request from a host for creation of a zone of memory; in response to the request, create the zone to avoid overprovisioning the zone; determine speed grades of a plurality of usage modes of the zone; inform the host of the speed grades of the plurality of usage modes of the zone; and receive, from the host, a command to write data in the zone pursuant to one of the plurality of usage modes. Other embodiments are provided.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: July 5, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventor: Dinesh Kumar Agarwal
  • Patent number: 11367014
    Abstract: An entangled quantum cache includes a quantum store that receives a plurality of quantum states and is configured to store and order the plurality of quantum states and to provide select ones of the stored and ordered plurality of quantum states to a quantum data output at a first desired time. A fidelity system is configured to determine a fidelity of at least some of the plurality of quantum states. A classical store is coupled to the fidelity system and configured to store classical data comprising the determined fidelity information and an index that associates particular ones of classical data with particular ones of the plurality of quantum states and to supply at least some of the classical data to a classical data output at a second desired time. A processor is connected to the classical store and determines the first time based on the index.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: June 21, 2022
    Assignee: Qubit Moving and Storage, LLC
    Inventors: Gary Vacon, Kristin A. Rauschenbach
  • Patent number: 11307792
    Abstract: An information processing apparatus includes: a memory; and a processor coupled to the memory and configured to: perform control to store data on the memory; determine a correlation between a plurality of pieces of data, based on pieces of attribute information of the plurality of pieces of data, wherein dispose pieces of data having a high correlation among the plurality of pieces of data at neighboring locations on the memory.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: April 19, 2022
    Assignee: FUJITSU LIMITED
    Inventor: Taketoshi Yoshida
  • Patent number: 11294573
    Abstract: Provided are a computer program product, system, and method for generating node access information for a transaction accessing nodes of a data set index. Pages in the memory are allocated to internal nodes and leaf nodes of a tree data structure representing all or a portion of a data set index for the data set. A transaction is processed with respect to the data set that involves accessing the internal and leaf nodes in the tree data structure, wherein the transaction comprises a read or write operation. Node access information is generated in transaction information, for accessed nodes comprising nodes in the tree data structure accessed as part of processing the transaction. The node access information includes a pointer to the page allocated to the accessed node prior to the transaction in response to the node being modified during the transaction.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: April 5, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Derek L. Erdmann, David C. Reed, Thomas C. Reed, Max D. Smith
  • Patent number: 11281579
    Abstract: Technologies for cryptographic separation of MMIO operations with an accelerator device include a computing device having a processor and an accelerator. The processor establishes a trusted execution environment. The accelerator determines, based on a target memory address, a first memory address range associated with the memory-mapped I/O transaction, generates a second authentication tag using a first cryptographic key from a set of cryptographic keys, wherein the first key is uniquely associated with the first memory address range. An accelerator validator determines whether the first authentication tag matches the second authentication tag, and a memory mapper commits the memory-mapped I/O transaction in response to a determination that the first authentication tag matches the second authentication tag. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: March 22, 2022
    Assignee: INTEL CORPORATION
    Inventors: Luis S. Kida, Reshma Lal, Soham Jayesh Desai
  • Patent number: 11269764
    Abstract: A storage system and method for adaptive scheduling of background operations are provided. In one embodiment, after a storage system completes a host operation in the memory, the storage system remains in a high power mode for a period of time, after which the storage system enters a low-power mode. The storage system estimates whether there will be enough time to perform a background operation in the memory during the period of time without the background operation being interrupted by another host operation. In response to estimating that there will be enough time to perform the background operation in the memory without the background operation being interrupted by another host operation, the storage system performs the background operation in the memory.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: March 8, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Judah Gamliel Hahn, Alexander Bazarsky, Ariel Navon, David Gur