Patents Examined by Andrew J Cheong
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Patent number: 10346261Abstract: There is provided a data distribution storing method including: recognizing, by a cluster manager managing a cluster of a plurality of nodes, a vehicle storage installed in a vehicle; transmitting, by the cluster manager, a vehicle index request including identification information about the vehicle storage to an index server; receiving, by the cluster manager, a first vehicle index including information about a first time section during which first vehicle data is recorded in the vehicle storage from the index server; selecting, by the cluster manager, a node from the cluster; transmitting, by the vehicle storage, second vehicle data recorded in the vehicle storage during a second time section which is after the first time section, to the node; generating, by the cluster manager, a second vehicle index based on the first vehicle index and information about the second time section and the node.Type: GrantFiled: October 11, 2016Date of Patent: July 9, 2019Assignee: HANWHA TECHWIN CO., LTD.Inventors: Durga Prasad Jujjuru, Joon Young Kim, Sek Rai Hong, Eun Min Kim
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Patent number: 10310979Abstract: A data processing system, having two or more of processors that access a shared data resource, and method of operation thereof. Data stored in a local cache is marked as being in a ‘UniqueDirty’, ‘SharedDirty’, ‘UniqueClean’, ‘SharedClean’ or ‘Invalid’ state. A snoop filter monitors access by the processors to the shared data resource, and includes snoop filter control logic and a snoop filter cache configured to maintain cache coherency. The snoop filter cache does not identify any local cache that stores the block of data in a ‘SharedDirty’ state, resulting in a smaller snoop filter cache size and simple snoop control logic. The data processing system by be defined by instructions of a Hardware Description Language.Type: GrantFiled: November 13, 2018Date of Patent: June 4, 2019Assignee: Arm LimitedInventors: Jamshed Jalal, Mark David Werkheiser
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Patent number: 10310765Abstract: Techniques for storing data on distributed data storage system are disclosed herein. A plurality of data shards are generated from data provided in association with a request to store the data. A first data shard having is generated from a first portion of the data and a second data shard is generated from a second portion of the data. An initial portion of the second data shard is appended or concatenated to the first data shard to generate an augmented first data shard. The augmented first data shard is stored on one or more storage nodes. The first and second data shards comprise a plurality of data records separated by record delimiters. Each data shard may filter record data contained thereon without coordination with other data shards based on positions of the record delimiters.Type: GrantFiled: August 31, 2017Date of Patent: June 4, 2019Assignee: Amazon Technologies, Inc.Inventor: Douglas Stewart Laurence
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Patent number: 10270773Abstract: One or more transactions may request or be assigned tokens within a transactional memory environment. A transaction may be created by at least one thread. A first transaction that includes a first token type may be received. A request may be received for a for a potential conflict check between the first transaction and a second transaction. In response to receiving the transaction potential conflict check, the first transaction and the second transaction are determined to be conflicting or not conflicting. The second transaction is assigned a token type in response to the determination of the transaction potential conflict check between the first transaction and the second transaction.Type: GrantFiled: November 4, 2015Date of Patent: April 23, 2019Assignee: International Business Machines CorporationInventors: Jonathan D. Bradbury, Fadi Y. Busaba, Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum
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Patent number: 10270775Abstract: One or more transactions may request or be assigned tokens within a transactional memory environment. A transaction may be created by at least one thread. A first transaction that includes a first token type may be received. A request may be received for a for a potential conflict check between the first transaction and a second transaction. In response to receiving the transaction potential conflict check, the first transaction and the second transaction are determined to be conflicting or not conflicting. The second transaction is assigned a token type in response to the determination of the transaction potential conflict check between the first transaction and the second transaction.Type: GrantFiled: May 3, 2016Date of Patent: April 23, 2019Assignee: International Business Machines CorporationInventors: Jonathan D. Bradbury, Fadi Y. Busaba, Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum
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Patent number: 10261703Abstract: Sharing read-only data among virtual machines (VM) using an attached coherent accelerator processor interface (CAPI) enabled flash storage (CeFS) is provided. The method includes mapping a file, by a virtual machine monitor, from the CeFS into a range of common memory in the virtual machine monitor. The VM shares the mapped file with at least one other VM at a range of common memory in their address spaces. A redirect-on-write filesystem (RoWFS) is created on the VM and the at least one other VM, whereby the RoWFS includes a read-only copy and a private copy of a linear memory map of the mapped file. A data page is read using the copy of the linear memory map, and the data page is modified using the private copy of the linear memory map.Type: GrantFiled: December 10, 2015Date of Patent: April 16, 2019Assignee: International Business Machines CorporationInventors: Gaurav Batra, Anil Kumar K. Damodaran, Douglas Griffith, Amarendar N. Sulu
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Patent number: 10255189Abstract: A transactional memory execution environment receives a first request from a first transaction to access a cache line. A first request is received from a first transaction to access a cache line. The cache line is determined to be used by a second transaction. The first transaction and the second transaction opt-in to a transaction potential conflict check. The transaction potential conflict check determines if the first transaction and the second transaction are in a conflicting coherent state. The conflicting coherent state occurs when the first transaction is modifying the cache line used by the second transaction. The first transaction is allowed access to the cache line without aborting the second transaction in response to a determination that the first transaction and the second transaction are compatible from the transaction potential conflict check.Type: GrantFiled: May 3, 2016Date of Patent: April 9, 2019Assignee: International Business Machines CorporationInventors: Jonathan D. Bradbury, Fadi Y. Busaba, Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum
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Patent number: 10235297Abstract: A transactional memory execution environment receives a first request from a first transaction to access a cache line. A first request is received from a first transaction to access a cache line. The cache line is determined to be used by a second transaction. The first transaction and the second transaction opt-in to a transaction potential conflict check. The transaction potential conflict check determines if the first transaction and the second transaction are in a conflicting coherent state. The conflicting coherent state occurs when the first transaction is modifying the cache line used by the second transaction. The first transaction is allowed access to the cache line without aborting the second transaction in response to a determination that the first transaction and the second transaction are compatible from the transaction potential conflict check.Type: GrantFiled: November 4, 2015Date of Patent: March 19, 2019Assignee: International Business Machines CorporationInventors: Jonathan D. Bradbury, Fadi Y. Busaba, Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum
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Patent number: 10235399Abstract: Methods and systems for enabling sizing of storage array resources are provided. Resources of a storage array can include, for example, cache, memory, SSD cache, central processing unit (CPU), storage capacity, number of hard disk drives (HDD), etc. Generally, methods and systems are provided that enable efficient predictability of sizing needs for said storage resources using historical storage array use and configuration metadata, which is gathered over time from an install base of storage arrays. This metadata is processed to produce models that are used to predict resource sizing needs to be implemented in storage arrays with certainty that takes into account customer-to-customer needs and variability. The efficiency in which the sizing assessment is made further provides significant value because it enables streamlining and acceleration of the provisioning process for storage arrays.Type: GrantFiled: November 4, 2015Date of Patent: March 19, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: David Adamson, Larry Lancaster
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Patent number: 10228856Abstract: A storage space management system for a thin provisioned virtual environment may comprise an over-allocation computation engine to compute an over-allocation metric for a virtual datastore. The over-allocation metric may be computed based on virtual storage space allocated to corresponding virtual machines and actual physical storage allocated to the virtual datastore. Further, the over-allocation metric may indicate extent of over-allocation of the actual physical storage to the virtual datastore. An available space computation engine may determine an available space metric for the virtual machines based on available datastore space and available physical storage space. An analysis engine may obtain a time value indicating time left within which storage space available for the virtual machines would be utilized.Type: GrantFiled: January 17, 2017Date of Patent: March 12, 2019Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: Vikram Krishnamurthy, Vijay Ram Sevagapandian, Abhijit Chaudhuri
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Patent number: 10216536Abstract: Memory data for a virtual machine can be stored in a swap file, which is comprised of storage blocks. A defragmentation procedure can be performed on a thin swap file while the virtual machine is still running. The described defragmentation procedure traversing a page frame space of the virtual machine, identifying candidate page frames, relocating the swapped page, and updating the page frame. Resulting unused storage blocks are released to the storage system. A data structure for aiding the defragmentation process is also described.Type: GrantFiled: March 11, 2016Date of Patent: February 26, 2019Assignee: VMware, Inc.Inventors: Ishan Banerjee, Preeti Agarwal, Jui-Hao Chiang
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Patent number: 10157133Abstract: A data processing system, having two or more of processors that access a shared data resource, and method of operation thereof. Data stored in a local cache is marked as being in a ‘UniqueDirty’, ‘SharedDirty’, ‘UniqueClean’, ‘SharedClean’ or ‘Invalid’ state. A snoop filter monitors access by the processors to the shared data resource, and includes snoop filter control logic and a snoop filter cache configured to maintain cache coherency. The snoop filter cache does not identify any local cache that stores the block of data in a ‘SharedDirty’ state, resulting in a smaller snoop filter cache size and simple snoop control logic. The data processing system by be defined by instructions of a Hardware Description Language.Type: GrantFiled: December 10, 2015Date of Patent: December 18, 2018Assignee: Arm LimitedInventors: Jamshed Jalal, Mark David Werkheiser
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Patent number: 10126980Abstract: When a request is received to perform a data operation requiring an interaction with any one of multiple data replicas stored on one or more data storage devices and managed by a quorum-based data management protocol in which completion of a data update is reported to an initiator of the data update when acceptance of the data update is reported by a majority of the data replicas, the data operation is routed to be performed using one of a predefined minority of the data replicas if the data operation requires less than strong consistency, is a read-only data operation, and meets a predefined criterion of being computationally time-intensive or computationally resource-intensive, or routed to be performed using a predefined majority of the data replicas if the data operation requires strong consistency or requires a data write operation or does not meet the predefined criterion.Type: GrantFiled: April 29, 2015Date of Patent: November 13, 2018Assignee: International Business Machines CorporationInventors: Guy Laden, Benjamin Mandler, Yoav Tock
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Patent number: 10114589Abstract: Apparatuses, systems, and methods are disclosed for controlling commands for non-volatile memory. An apparatus includes one or more memory die. A memory die includes a command/address buffer, an on-die controller, and a plurality of non-volatile memory cores that share a data path. A core includes an array of non-volatile memory cells. A command/address buffer queues command and address information for a plurality of storage operations for one or more non-volatile memory cores. An on-die controller initiates a first unexecuted read operation and a first unexecuted write operation from a command/address buffer in parallel, in response to determining that core dependencies are satisfied for a read operation and a write operation.Type: GrantFiled: January 17, 2017Date of Patent: October 30, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Jingwen Ouyang, Greg Hilton, Jayesh Pakhale
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Patent number: 10108548Abstract: In one aspect, a processor has a register file, a private Level 1 (L1) cache, and an interface to a shared memory hierarchy (e.g., an Level 2 (L2) cache and so on). The processor has a Load Store Unit (LSU) that handles decoded load and store instructions. The processor may support out of order and multi-threaded execution. As store instructions arrive at the LSU for processing, the LSU determines whether a counter, from a set of counters, is allocated to a cache line affected by each store. If not, the LSU allocates a counter. If so, then the LSU updates the counter. Also, in response to a store instruction, affecting a cache line neighboring a cache line that has a counter that meets a criteria, the LSU characterizes that store instruction as one to be effected without obtaining ownership of the effected cache line, and provides that store to be serviced by an element of the shared memory hierarchy.Type: GrantFiled: August 18, 2015Date of Patent: October 23, 2018Assignee: MIPS Tech, LLCInventors: Ranjit J. Rozario, Era Nangia, Debasish Chandra, Ranganathan Sudhakar
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Patent number: 10078470Abstract: A signal transfer device includes an interface and a read and write circuit. The interface has a posted write data protocol and transfers data to a memory control device that controls access to a shared memory. If a write request for writing data to the shared memory via the interface is issued, the read and write circuit acquires a write address from the write request, and puts a read request for reading data from the write address on standby until a transfer amount of write data exceeds a total size of buffers on a signal transfer path to the shared memory.Type: GrantFiled: February 29, 2016Date of Patent: September 18, 2018Assignee: Ricoh Company, Ltd.Inventor: Masahiro Suzuki
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Patent number: 10078594Abstract: A computer manages a cache for a MapReduce application based on a distributed file system that includes one or more storage medium by receiving a map request and receiving parameters for processing the map request. The parameters include a total data size to be processed, a size of each data record, and a number of map requests executing simultaneously. The computer determines a cache size for processing the map request, wherein the cache size is determined based on the received parameters for processing the map request and a machine learning model for a map request cache size and reads, based on the determined cache size, data from the one or more storage medium of the distributed file system into the cache. The computer processes the map request and writes an intermediate result data of the map request processing into the cache, based on the determined cache size.Type: GrantFiled: August 18, 2015Date of Patent: September 18, 2018Assignee: International Business Machines CorporationInventors: Liang Liu, Junmei Qu, ChaoQiang Zhu, Wei Zhuang
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Patent number: 10037276Abstract: The disclosed computer-implemented method for accelerating access to data may include (1) monitoring, at a data-caching system, read requests of a first data-accessing system for a dataset managed by a data-management system, (2) identifying a pattern of the read requests of the first data-accessing system, (3) monitoring, at the data-caching system, read requests of a second data-accessing system for the dataset managed by the data-management system, (4) determining that a pattern of the read requests of the second data-accessing system resembles the pattern of the read requests of the first data-accessing system, and (5) using a portion of the dataset accessed by the read requests of the first data-accessing system to pre-warm a cache of the second data-accessing system. Various other methods, systems, and computer-readable media are also disclosed.Type: GrantFiled: November 4, 2015Date of Patent: July 31, 2018Assignee: Veritas Technologies LLCInventors: Chirag Dalal, Vaijayanti Bharadwaj, Pradip Kulkarni
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Patent number: 10019193Abstract: Methods, systems, and computer programs are presented for virtualizing Non-Volatile Random Access Memory (NVRAM). A first area in RAM is labeled as active area and a second area as non-active area, and an active journal and a non-active journal are created in permanent storage. A transaction is created for each write made to the virtual NVRAM, and the created transactions are written to the active journal and to the active area. When the active journal is greater than a predetermined size or a timeout occurs, a checkpoint is created by copying contents from the active area to the non-active area, switching status of the active area and the non-active areas (the active area becomes the non-active area and the non-active area becomes the active area), switching status of the active journal and the non-active journal, and copying the content of the current non-active area to permanent storage.Type: GrantFiled: November 4, 2015Date of Patent: July 10, 2018Assignee: Hewlett Packard Enterprise Development LPInventors: Xiaoshan Zuo, Tomasz Barszczak
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Patent number: 9864693Abstract: A data processing method executed by a processor included in an information processing device, the data processing method includes reserving a storage area of a memory when a reservation request is detected; acquiring a number of cache misses indicating that desired data is not capable of being read from a storage area to be accessed, the cache misses having occurred in response to a request for access to the storage area; and setting a new storage area so as to shift the new storage area from the reserved storage area when it is determined that the acquired number is larger than or equal to a given value.Type: GrantFiled: October 26, 2015Date of Patent: January 9, 2018Assignee: FUJITSU LIMITEDInventors: Yoshinori Sugisaki, Kiyofumi Suzuki