Abstract: Described herein is a technique capable of selectively growing a film with a high selectivity on a substrate with surface portions of different materials. According to one aspect of the technique of the present disclosure, there is provided a method of manufacturing a semiconductor device including: (a) forming a second metal film on a substrate with a first metal film and an insulating film formed thereon by alternately supplying a metal-containing gas and a reactive gas onto the substrate, wherein an incubation time on the insulating film is longer than that on the first metal film; and (b) supplying an etching gas onto the substrate to remove the second metal film formed on the insulating film while allowing the second metal film to remain on the first metal film, wherein the second metal film is selectively grown on the first metal film by alternately repeating (a) and (b).

Abstract: An etchant composition and a method of fabricating a semiconductor device, the composition including an inorganic acid; about 0.01 parts by weight to about 0.5 parts by weight of colloidal silica; about 0.01 parts by weight to about 30 parts by weight of an ammonium-based additive; and about 20 parts by weight to about 50 parts by weight of a solvent, all parts by weight being based on 100 parts by weight of the inorganic acid.

Abstract: A plasma etching method includes a physisorption step for causing an adsorbate that is based on first processing gas to be physisorbed onto a film to be etched, while cooling an object to be processed on which the film to be etched is provided; and an etching step for etching the film to be etched by causing the adsorbate to react with the film to be etched, using the plasma of second processing gas.

Abstract: An abrasive slurry composition for chemical mechanical planarization/polishing (CMP) is provided. The abrasive slurry includes colloidal alumina, a dispersant, and a pH buffer. The colloidal alumina has a particle size of between about 5 nm and about 100 nm. The colloidal alumina may be alpha phase material having a first hardness of about 9 Mohs, or gamma phase material having a second hardness of about 8 Mohs. The abrasive slurry may further include polyacrylic acid (PAA), a down-force enhancer, or a polish-rate inhibitor.

Abstract: An etching method which includes treating a workpiece having a stacked film (5) of a silicon oxide layer (2) and a silicon nitride layer (3) with an etching gas containing an unsaturated halon represented by the chemical formula: C2HxF(3?x)Br (in the chemical formula, x stands for 0, 1, or 2) so as to control the respective etch rates of the silicon nitride layer and the silicon oxide layer to the same level and form a high-aspect-ratio hole having a desirable profile at a high etch rate. Also disclosed is a method of manufacturing a semiconductor which includes by carrying out the etching method.

Abstract: A method of manufacturing a fiber ferrule assembly that includes inserting an exposed end portion of a plurality of optical fibers including a core and a cladding into an array of insertion holes disposed in a glass ferrule plate. The glass ferrule plate includes a glass material that differs from a glass material of both the core and the cladding. The method further includes chemically etching the glass ferrule plate and the exposed end portion of the plurality of optical fibers using a chemical etchant for an etching time period. The glass ferrule plate etches at a first etching rate, the exposed end portion etches at a second etching rate, and the first etching rate is faster than the second etching rate such that, after the etching time period, the exposed end portion of each of the plurality of optical fibers protrude from a second surface of the glass ferrule plate.

Abstract: A method of manufacturing a semiconductor device is provided, and the method may include: preparing a semiconductor substrate constituted of a group III nitride semiconductor, a main surface of the semiconductor substrate being a c-plane; forming a grove on the main surface by dry dry-etching the main surface; and wet-etching an inner surface of the groove using an etchant to expose the c-plane of the semiconductor substrate in a wet-etched region, the etching having an etching rate to the c-plane of the semiconductor substrate that is lower than the etching rate to a plane other than the c-plane of the semiconductor substrate.

Abstract: Devices, systems and techniques are described for producing and implementing articles and materials having nanoscale and microscale structures that exhibit superhydrophobic, superoleophobic or omniphobic surface properties and other enhanced properties. In one aspect, a surface nanostructure can be formed by adding a silicon-containing buffer layer such as silicon, silicon oxide or silicon nitride layer, followed by metal film deposition and heating to convert the metal film into balled-up, discrete islands to form an etch mask. The buffer layer can be etched using the etch mask to create an array of pillar structures underneath the etch mask, in which the pillar structures have a shape that includes cylinders, negatively tapered rods, or cones and are vertically aligned. In another aspect, a method of fabricating microscale or nanoscale polymer or metal structures on a substrate is made by photolithography and/or nano imprinting lithography.

Abstract: A method for etching silicon at cryogenic temperatures is provided. The method includes forming an inert layer from condensation of a noble gas at cryogenic temperatures on exposed surfaces such as the sidewalls of a feature to passivate the sidewalls prior to the etching process. The method further includes flowing a fluorine-containing precursor gas into the chamber to form a fluorine-containing layer on the inert layer. The method further includes exposing the fluorine-containing layer and the inert layer to an energy source to form a passivation layer on the exposed portions of the substrate and exposing the substrate to ions to etch the substrate.

Abstract: There is provided a technique that includes: (a) loading a substrate including a base and a first film containing silicon and formed on the base into a process container; (b) converting a modifying gas containing helium into plasma to generate reactive species of helium; and (c) supplying the modifying gas containing the reactive species of helium to a surface of the substrate to respectively modify the first film and an interface layer of the base constituting an interface with the first film.

Abstract: Methods for polishing semiconductor substrates that involve adjusting the finish polishing sequence based on the pad-to-pad variance of the polishing pad are disclosed.

Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Abstract: A method may include providing a set of features in a mask layer, wherein a given feature comprises a first dimension along a first direction, second dimension along a second direction, orthogonal to the first direction, and directing an angled ion beam to a first side region of the set of features in a first exposure, wherein the first side region is etched a first amount along the first direction. The method may include directing an angled deposition beam to a second side region of the set of features in a second exposure, wherein a protective layer is formed on the second side region, the second side region being oriented perpendicularly with respect to the first side region. The method may include directing the angled ion beam to the first side region in a third exposure, wherein the first side region is etched a second amount along the first direction.

Abstract: The invention relates to the chemical etching of a semiconductor material, including: deposition at least one mask (PLP) on a first surface zone of a semiconductor material (SC); and chemically etching (S31) a second surface zone of the semiconductor material (SC) that is not covered by the mask (PLP). In particular, the aforementioned mask is produced in a material including polyphosphazene, which material protects the underlying semiconductor especially well.

Abstract: There is provided a technique that includes partially etching a film formed on a surface of a substrate by performing a cycle a predetermined number of times, the cycle including: (a) setting a temperature of the substrate having the first film formed on the surface to a first temperature; (b) stabilizing an in-plane temperature of the substrate at the first temperature; and (c) lowering the temperature of the substrate having the in-plane temperature stabilized at the first temperature from the first temperature to a second temperature that is lower than the first temperature, wherein in (c), an etching gas is supplied to the substrate for a predetermined period.

Abstract: A robust and general fabrication/manufacturing method is described herein for the fabrication of periodic three-dimensional (3D) hierarchical nanostructures in a highly scalable and tunable manner. This nanofabrication technique exploits the selected and repeated etching of spherical particles that serve as resist material and that can be shaped in parallel for each processing step. The method enables the fabrication of periodic, vertically aligned nanotubes at the wafer scale with nanometer-scale control in three dimensions including outer/inner diameters, heights/hole-depths, and pitches. The method was utilized to construct 3D periodic hierarchical hybrid silicon and hybrid nanostructures such as multi-level solid/hollow nanotowers where the height and diameter of each level of each structure can be configured precisely as well as 3D concentric plasmonic supported metal nanodisk/nanorings with tunable optical properties on a variety of substrates.

Abstract: In a plasma processing method, a substrate is loaded onto a lower electrode within a chamber. A plasma power is applied to form plasma within the chamber. A voltage function of a nonsinusoidal wave having a DC pulse portion and a ramp portion is generated. Generating the voltage function may include setting a slope of the ramp portion and setting a duration ratio of the ramp portion to a cycle of the voltage function in order to control an ion energy distribution generated at a surface of the substrate. A bias power of the nonsinusoidal wave is applied to the lower electrode.

Abstract: Disclosed is a method of etching a metal barrier layer and a metal layer. The method includes forming the metal barrier layer and the metal layer on a substrate, and using an etching composition to etch the metal barrier layer and the metal layer. The etching composition may include an oxidant selected from nitric acid, bromic acid, iodic acid, perchloric acid, perbromic acid, periodic acid, sulfuric acid, methane sulfonic acid, p-toluenesulfonic acid, benzenesulfonic acid, or a combination thereof, a metal etching inhibitor including a compound expressed by Chemical Formula 1, and a metal oxide solubilizer selected from phosphoric acid, phosphate, carboxylic acid having 3 to 20 carbon atoms, or a combination thereof.

Abstract: Methods for forming an electrode structure, which can be used as a biosensor, are provided in which the electrode structure has non-random topography located on one surface of an electrode base. In some embodiments, an electrode structure is obtained that contains no interface between the non-random topography of the electrode structure and the electrode base of the electrode structure. In other embodiments, electrode structures are obtained that have an interface between the non-random topography of the electrode structure and the electrode base of the electrode structure.

Abstract: Enhanced compositions and methods are provided for selectively etching silicon wafers, which is particularly useful in the context of silicon wafer manufacturing and processing applications. Optionally, a formulation is provided which selectively etches silicon dioxide in preference to aluminum oxide. Optionally, a formulation and method are provided that is substantially non-aqueous.