Abstract: A method of processing materials on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules is provided. A workpiece having an upper planar surface is received into the common manufacturing platform. The method further includes conformally applying a thin film over the feature pattern using one of the film-forming modules, removing the thin film from upper surfaces of the feature pattern using one of the etching modules to leave behind the thin film in the recessed feature, and removing the fill material from the upper planar surface of the workpiece. The integrated sequence of processing steps is executed in a controlled environment within the common manufacturing platform and without leaving the controlled environment.

Abstract: A plasma sputtering device including one or a plurality of plasma generating devices each including an insulating tube having an expanding inner diameter and having a gas injection port formed in an end portion or a side portion thereof, a first electromagnet or a permanent magnet group which can apply a static magnetic field, and a high frequency antenna; a second electromagnet which is disposed in a region downstream of the plasma generating device(s) and which can form a curved magnetic force line structure; a target mechanism which includes a permanent magnet embedded therein and a cooling mechanism and which can apply a DC or high frequency voltage; a substrate stage facing the target mechanism; a second permanent magnet group around the substrate stage; and a heat insulating mechanism between a target material and the target mechanism.

Abstract: A method and apparatus for of improving processing results in a processing chamber by orienting a substrate support relative to a surface within the processing chamber. The method comprising orienting a supporting surface of a substrate support in a first orientation relative to an output surface of a showerhead, where the first orientation of the supporting surface relative to the output surface is not coplanar, and depositing a first layer of material on a substrate disposed on the supporting surface that is oriented in the first orientation.

Abstract: A method of reconstructing a characteristic of a structure formed on a substrate by a lithographic process, and an associated metrology apparatus. The method includes combining measured values of a first parameter associated with the lithographic process to obtain an estimated value of the first parameter; and reconstructing at least a second parameter associated with the characteristic of the structure using the estimated value of the first parameter and a measurement of the structure. The combining may involve modeling a variation of the first parameter to obtain a parameter model or fingerprint of the first parameter.

Abstract: A method is for manufacturing a magnetic-tunnel-junction (MTJ) device. The method includes forming a free magnetic layer over a substrate, forming a metal layer over the free magnetic layer, and oxidizing the metal layer by exposing the metal layer to an oxidation gas at a temperature of 250° K or less.

Abstract: A method includes forming a dummy gate structure over a semiconductor fin, forming a dielectric layer on opposing sides of the dummy gate structure, and removing the dummy gate structure to form a recess in the dielectric layer. The method further includes forming a gate dielectric layer and at least one conductive layer successively over sidewalls and a bottom of the recess, and treating the gate dielectric layer and the at least one conductive layer with a chemical containing fluoride (F).

Abstract: A semiconductor device comprises a memory storage component and a transistor in operable communication with the memory storage element. The transistor comprises a source region, a drain region, a gate electrode between the source region and the drain region, a charge trapping material surrounding at least an upper portion of the gate electrode, and an oxide material on sides of the charge trapping material. Related systems and methods are also disclosed.

Abstract: The present disclosure provides a display panel, a manufacturing method of a display panel, and a display device including the display panel. The display panel includes: an array substrate, including a display region, a non-display region around the display region, and data lines extending into the non-display region; a planarization layer, covering the data lines; and a metal wiring layer, disposed on the planarization layer in the non-display region, and including a plurality of metal wirings spaced apart from each other and corresponding to the data lines.

Abstract: Provided is a method for forming an epitaxial layer at a low temperature. The method for forming the epitaxial layer includes transferring a substrate into an epitaxial chamber and performing an epitaxial process on the substrate to form an epitaxial layer on the substrate. The epitaxial process includes heating the substrate at a temperature of about 700° C. or less and injecting a silicon gas into the epitaxial chamber in a state in which the inside of the epitaxial chamber is adjusted to a pressure of about 300 Torr or less to form a first epitaxial layer, stopping the injection of the silicon gas and injecting a purge gas into the epitaxial chamber to perform first purge inside the epitaxial chamber, heating the substrate at a temperature of about 700° C.

Abstract: Reflective bank structures for light emitting devices are described. The reflective bank structure may include a substrate, an insulating layer on the substrate, and an array of bank openings in the insulating layer with each bank opening including a bottom surface and sidewalls. A reflective layer spans sidewalls of each of the bank openings in the insulating layer.

Abstract: An insulated gate semiconductor device includes p+ gate bottom protection regions embedded in a drift layer at the bottoms of trenches that goes through n+ source regions and p-type base regions, and p+ base bottom embedded regions embedded in the drift layer below the base regions. The base bottom embedded regions have trapezoidal shapes due to a channeling phenomenon, and the bottom surfaces of the base bottom embedded regions are deeper than the bottom surfaces of the gate bottom protection regions.

Abstract: A method for contacting a metallic contact pad embedded in a printed circuit board layer sequence, comprising the steps of producing a first hole matrix having a plurality of holes in a surface of the printed circuit board layer sequence in order to partly expose the metallic contact pad, of applying a metal layer in order to at least partly fill the holes of the first hole matrix, of producing a second hole matrix having a plurality of holes in the surface of the printed circuit board layer sequence in order to partly expose the metallic contact pad, wherein the holes of the second hole matrix are arranged in a manner offset relative to the holes of the first hole matrix, and of applying a metal layer in order to at least partly fill the holes of the second hole matrix, and a correspondingly produced printed circuit board.

Abstract: A semiconductor device and a method of forming the same are provided. In one embodiment, the semiconductor device includes a semiconductor substrate, a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions, and a plurality of gate structures. The plurality of gate structures includes an interfacial layer (IL) disposed over the plurality of channel regions, a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region, a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and a third high-k dielectric layer disposed over the plurality of channel regions. The first, second and third high-k dielectric layers are different from one another.

Abstract: There is provided a nitride semiconductor substrate, including: a substrate configured as an n-type semiconductor substrate; and a drift layer provided on the substrate and configured as a gallium nitride layer containing donors and carbons, wherein a concentration of the donors in the drift layer is 5.0×1016/cm3 or less, and is equal to or more than a concentration of the carbons that function as acceptors in the drift layer, over an entire area of the drift layer, and a difference obtained by subtracting the concentration of the carbons that function as acceptors in the drift layer from the concentration of the donors in the drift layer, is gradually increased from a substrate side toward a surface side of the drift layer.

Abstract: A display device includes a display panel having a first region, a second region spaced apart from the first region, and a bending region between the first region and the second region, the bending region being bent along a bending axis, a protective film including a first part on a first surface of the first region of the display panel, the first part having an opening at a center thereof that exposes the first surface of the display panel, and a second part on a first surface of the second region of the display panel, and a functional layer on the first surface of the display panel exposed by the opening.

Abstract: A method for forming a film with an annealing step and a deposition step is disclosed. The method comprises an annealing step for inducing self-assembly or alignment within a polymer. The method also comprises a selective deposition step in order to enable selective deposition on a polymer.

Abstract: Photovoltaic cells, photovoltaic devices, and methods of fabrication are provided. The photovoltaic cells include a transparent substrate to allow light to enter the photovoltaic cell through the substrate, and a light absorption layer associated with the substrate. The light absorption layer has opposite first and second surfaces, with the first surface being closer to the transparent substrate than the second surface. A passivation layer is disposed over the second surface of the light absorption layer, and a plurality of first discrete contacts and a plurality of second discrete contacts are provided within the passivation layer to facilitate electrical coupling to the light absorption layer. A first electrode and a second electrode are disposed over the passivation layer to contact the plurality of first discrete contacts and the plurality of second discrete contacts, respectively. The first and second electrodes may include a photon-reflective material.

Abstract: A flexible display device includes a flexible display panel having a bending area to be folded, and including a display substrate, and a thin-film encapsulation layer above the display substrate, a driving portion, and a function layer below the flexible display panel, and including a step portion below which the flexible display panel is electrically connected to the driving portion.

Abstract: Embodiments are directed to a sensor having a first electrode, a second electrode and a detector region electrically coupled between the first electrode region and the second electrode region. The detector region includes a first layer having a topological insulator. The topological insulator includes a conducting path along a surface of the topological insulator, and the detector region further includes a second layer having a first insulating magnetic coupler, wherein a magnetic field applied to the detector region changes a resistance of the conducting path.

Abstract: Embodiments of packaged semiconductor devices and lead frames for such devices are provided, such as a lead frame including: a row of lead fingers, wherein an outer end of each lead finger is connected to a leaded side of the lead frame; a package body perimeter that indicates placement of a package body of the packaged semiconductor device, wherein an inner end of each lead finger falls within the package body perimeter; a retention tab that protrudes from an interior edge of a non-leaded side of the lead frame, wherein the retention tab falls outside of the package body perimeter; and a non-conductive tie bar structure attached to the retention tab, wherein the non-conductive tie bar structure falls within the package body perimeter.