Abstract: A method of fabricating a semiconductor device includes forming a buried insulation region within a substrate by processing the substrate using etching and deposition processes. A semiconductor layer is formed over the buried insulation region at a first side of the substrate. Device regions are formed in the semiconductor layer. The substrate is thinned from a second side of the substrate to expose the buried insulation region. The buried insulation region is selectively removed to expose a bottom surface of the substrate. A conductive region is formed under the bottom surface of the substrate.

Abstract: Integrated circuits for a single-molecule nucleic-acid assay platform, and methods for making such circuits are disclosed. In one example, a method includes transferring one or more carbon nanotubes to a complementary metal-oxide semiconductor (CMOS) substrate, and forming a pair of post-processed electrodes on the substrate proximate opposing ends of the one or more carbon nanotubes.

Abstract: A display device includes: a display element; a wavelength conversion element disposed on the display element and comprising a plurality of first wavelength conversion layers and a plurality of second wavelength conversion layers arranged in a first predetermined pattern; a transparent frame disposed on the wavelength conversion element and having a plurality of air gaps defined on a surface facing the wavelength conversion element, wherein the air gaps are recessed in a thickness direction; and a color filter element disposed on the transparent frame and comprising a plurality of first wavelength filter layers, a plurality of second wavelength filter layers and a plurality of third wavelength filter layers arranged in a second predetermined pattern, wherein the first and second wavelength filter layers are arranged to overlap the first and second wavelength conversion layers, respectively, and wherein the air gaps are arranged to overlap the first and second wavelength conversion layers.

Abstract: In a semiconductor component or device, a lateral power effect transistor is produced as an LDMOS transistor in such a way that, in combination with a trench isolation region (12) and the heavily doped feed guiding region (28, 28A), an improved potential profile is achieved in the drain drift region (8) of the transistor. For this purpose, in advantageous embodiments, it is possible to use standard implantation processes of CMOS technology, without additional method steps being required.

Abstract: There is provided a method of forming a boron film on a substrate on which a semiconductor device is formed, by plasmarizing a reaction gas containing a boron-containing gas under a process atmosphere regulated to a pressure which falls within a range of 0.67 to 33.3 Pa (5 to 250 mTorr). The boron film is formed on a substrate on which a semiconductor device is formed, by plasmarizing a reaction gas containing a boron-containing gas under a process atmosphere regulated to a pressure which falls within a range of 0.67 to 33.3 Pa (5 to 250 mTorr).

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Abstract: A semiconductor structure comprises a first conductive material-containing layer. The first conductive material-containing layer comprises a dielectric material, at least two conductive structures in the dielectric material, and an air-gap region in the dielectric material between the at least two conductive structures. The semiconductor structure also comprises a capping layer over the at least two conductive structures and the air-gap region. The semiconductor structure further comprises a second conductive material-containing layer over the capping layer. The second conductive material-containing layer comprises a via plug electrically connected to one of the at least two conductive structures. The via plug is separated from the air-gap region by at least a first predetermined distance. The semiconductor structure additionally comprises a conductive pad over the second conductive material-containing layer. The conductive pad is offset from the air-gap region by at least a second predetermined distance.

Abstract: A method of forming a gate-all-around semiconductor device, includes providing a substrate having a layered fin structure thereon. The layered fin structure includes a channel portion and a sacrificial portion each extending along a length of the layered fin structure, wherein the layered fin structure being covered with replacement gate material. A dummy gate is formed on the replacement gate material over the layered fin structure, wherein the dummy gate having a critical dimension which extends along the length of the layered fin structure. The method further includes forming a gate structure directly under the dummy gate, the gate structure including a metal gate region and gate spacers provided on opposing sides of the metal gate region, wherein a total critical dimension of the gate structure is equal to the critical dimension of the dummy gate.

Abstract: Apparatus and methods of forming an apparatus can include one or more cell contacts in an integrated circuit in a variety of applications. In various embodiments, a resist underlayer can be formed on a dielectric spacer formed on a structure for a cell contact, where the structure can include a patterned area of pillars on a silicon-rich dielectric anti-reflective coating region disposed on a dielectric region. The resist underlayer, the dielectric spacer, the patterned area of pillars, the silicon-rich dielectric anti-reflective coating, and the dielectric region can be processed to form an array of columns in the dielectric region. Regions between the columns of the array of columns can be filled with conductive material, forming the cell contact. Additional apparatus, systems, and methods are disclosed.

Abstract: A semiconductor device includes a semiconductor element, a base, and an outer packaging resin. The base has a mounting surface, on which the semiconductor element is mounted, and a groove provided around the semiconductor element on the mounting surface. An outer packaging resin covers the semiconductor element and the base, and is fixed to the base by filling the groove. A bottom of the groove includes a first recess-projection having a first amplitude and a first repetition interval along an extending direction of the groove. The first recess-projection includes a second recess-projection having a second amplitude smaller than the first amplitude and a second repetition interval shorter than the first repetition interval along the extending direction of the groove.

Abstract: The present invention relates to a vertical semiconductor device such as an IGBT or a diode which includes an N buffer layer formed in the undersurface of and adjacent to an N? drift layer. A concentration slope ?, which is derived from displacements in a depth TB (?m) and an impurity concentration CB (cm?3), from the upper surface to the lower surface in a main portion of the N buffer layer satisfies a concentration slope condition defined by {0.03???0.7}.

Abstract: To improve detection efficiency in a solid-state imaging element including a SPAD in which an electrode and wiring are placed in a central portion. A solid-state imaging element includes a photodiode and a light collecting section. The photodiode includes a light receiving surface and an electrode placed on the light receiving surface, and that outputs an electrical signal in accordance with light incident on the light receiving surface in a state where a voltage exceeding a breakdown voltage is applied to the electrode. The light collecting section causes light from a subject to be collected in the light receiving surface other than a region where the electrode is placed.

Abstract: A method for manufacturing a flexible electrical device is provided and includes the following steps. A carrier substrate is provided. A releasing layer is formed on the carrier substrate. A flexible substrate is formed on the releasing layer. The flexible substrate has a first surface facing the releasing layer and a second surface opposite to the first surface. The flexible substrate is not in contact with the carrier substrate. A device layer is formed on the flexible substrate. The device layer has a third surface facing the flexible substrate and a fourth surface opposite to the third surface. The flexible substrate is separated from the releasing layer, and the releasing layer remains on the carrier substrate. Accordingly, the releasing layer and the carrier substrate can be recycled for forming another flexible electrical device.

Abstract: The present invention provides a method for manufacturing a semiconductor device including following steps. A substrate, a hard mask layer disposed on the substrate and a first mask pattern disposed on the hard mask layer are provided, and the substrate has a device region and a cutting line region. The first mask pattern has first gaps in the device region and second gaps in the cutting line region. Next, a spacer layer conformally covers the first mask pattern. Then, a second mask pattern is formed on the spacer layer in the first gaps, and a top surface of the second mask pattern is lower than a top surface of the first mask pattern. Thereafter, an etching process is performed to the spacer layer to remove the spacer layer between the first mask layer and the second mask layer and in the second gaps and expose the hard mask layer.

Abstract: A method includes forming a dummy gate structure over a semiconductor fin, forming a dielectric layer on opposing sides of the dummy gate structure, and removing the dummy gate structure to form a recess in the dielectric layer. The method further includes forming a gate dielectric layer and at least one conductive layer successively over sidewalls and a bottom of the recess, and treating the gate dielectric layer and the at least one conductive layer with a chemical containing fluoride (F).

Abstract: A die includes a metal pad, a passivation layer over the metal pad, and a polymer layer over the passivation layer. A metal pillar is over and electrically coupled to the metal pad. A metal ring is coplanar with the metal pillar. The polymer layer includes a portion coplanar with the metal pillar and the metal ring.

Abstract: A method and apparatus for of improving processing results in a processing chamber by orienting a substrate support relative to a surface within the processing chamber. The method comprising orienting a supporting surface of a substrate support in a first orientation relative to an output surface of a showerhead, where the first orientation of the supporting surface relative to the output surface is not coplanar, and depositing a first layer of material on a substrate disposed on the supporting surface that is oriented in the first orientation.

Abstract: The heat sink is a body or block of solid-phase gallium having a plurality of sealed cavities defined therein containing an unencapsulated phase change material (other than gallium). The solid-phase gallium may be disposed in a container having at least one open face (contact face) adapted for direct contact with the heat source requiring cooling so that the interface between the heat source and the heat sink includes a region of melted gallium for improved heat transfer. Heat from the heat source is rapidly conducted through the region of melted gallium, then through solid-phase gallium, and is absorbed by the phase change material in the cavities without significant change in temperature, maintaining viability of the heat sink. The heat sink may include inclined tubes through the solid-phase body of gallium, the tubes being open at opposite ends for passage of a cooling medium, such as air or cold water.

Abstract: The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure include a hybrid orientation substrate having a first active region having a first crystallographic orientation that is vertically separated from a second active region having a second crystallographic orientation different than the first crystallographic orientation. A first field effect device having a first gate electrode is located and formed within and upon the first active region and a second field effect device having a second gate electrode is located and formed within and upon the second active region. Upper surfaces of the first gate electrode and the second gate electrode are coplanar. The structure and method allow for avoidance of epitaxial defects generally encountered when using hybrid orientation technology substrates that include coplanar active regions.