Abstract: A printed electronic device may comprise a plurality of contact pads arranged in a pattern, a plurality of electrode traces arranged in another pattern, the plurality of electrode traces comprising a set of bottom electrode traces and a set of top electrode traces, each electrode trace in electrical communication with an associated contact pad of the plurality of contact pads, and a plurality of memory cells, each memory cell located at an intersection of a pair of electrode traces of the plurality of electrode traces and comprising a bottom electrode layer formed from a region of one of the bottom electrode traces, a top electrode layer formed from a region of one of the top electrode traces, and a ferroelectric layer between the bottom and top electrode layers.

Abstract: Kesterite-based photovoltaic devices formed on flexible ceramic substrates are provided. In one aspect, a method of forming a photovoltaic device includes the steps of: forming a back contact on a flexible ceramic substrate; forming a kesterite absorber layer on a side of the back contact opposite the flexible ceramic substrate; annealing the kesterite absorber layer; forming a buffer layer on a side of the kesterite absorber layer opposite the back contact; and forming a transparent front contact on a side of the buffer layer opposite the kesterite absorber layer. A roll-to-roll-based method of forming a photovoltaic device and a photovoltaic device are also provided.

Abstract: Some embodiments include constructions which have platinum-containing structures. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures and across metal oxide. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures, across a first material retaining the platinum-containing structures, and across metal oxide liners along sidewalls of the platinum-containing structures and directly between the platinum-containing structures and the first material. Some embodiments include methods of forming platinum-containing structures. In some embodiments, first material is formed across electrically conductive structures, and metal oxide is formed across the first material. Openings are formed to extend through the metal oxide and the first material to the electrically conductive structures. Platinum-containing material is formed within the openings and over the metal oxide.

Abstract: A method of forming an array of elevationally-extending strings of memory cells comprises forming and removing a portion of lower-stack memory cell material that is laterally across individual bases in individual lower channel openings. Covering material is formed in a lowest portion of the individual lower channel openings to cover the individual bases of the individual lower channel openings. Upper channel openings are formed into an upper stack to the lower channel openings to form interconnected channel openings individually comprising one of the individual lower channel openings and individual of the upper channel openings. A portion of upper-stack memory cell material that is laterally across individual bases in individual upper channel openings is formed and removed. After the removing of the portion of the upper-stack memory cell material, the covering material is removed from the interconnected channel openings.

Abstract: Systems and methods for improved light emitting efficiency of a solid state transducer (SST), for example light emitting diodes (LED), are disclosed. One embodiment of an SST die in accordance with the technology includes a reflective material disposed over electrical connectors on a front side of the die. The reflective material has a higher reflectivity than a base material of the connectors such that light traveling toward the connectors reflects back out of the device.

Abstract: A press-fit pin increases contact area with the contact hole to provide appropriate contact pressure, reduce contact resistance, and increase heat transfer efficiency. The press-fit pin is of a semiconductor package including an end portion and a press unit extending from the end portion and is divided into a first press-fitting piece and a second press-fitting piece, the first press-fitting piece forming a convex portion in a first direction perpendicular to the direction of the press-fit pin and bending to a second direction perpendicular to the direction of the press-fit pin and forming 30-110 degrees with the first direction and the second press-fitting piece forming a convex portion in a third direction perpendicular to the direction of the press-fit pin and being 180 degrees with the first direction and bending to a fourth direction perpendicular to the direction of the press-fit pin and forming 250-330 degrees with the first direction.

Abstract: One embodiment of the disclosure relates to an unguarded Schottky barrier diode. The diode includes a cathode that has a recessed region and a dielectric interface surface that laterally extends around a perimeter of the recessed region. The diode further includes an anode that conforms to the recessed region. A dielectric layer extends over the dielectric interface surface of the cathode and further extends over a portion of the anode near the perimeter. Other devices and methods are also disclosed.

Abstract: Semiconductor devices and methods of forming thereof by post layer transfer fabrication of device isolation structures are described. A substrate with first and second major surfaces is provided. Circuit components may be formed on the first major surface of the substrate and a back-end-of-line (BEOL) dielectric layer is formed over the first major surface of the substrate which covers the circuit components. A single layer transfer is performed to expose the second major surface of the substrate for processing. The second major surface of the semiconductor substrate is processed to thin down the wafer, followed by a wafer thickness uniformity improvement process. One or more device isolation structures are formed through the semiconductor substrate from the second major surface of the semiconductor substrate.

Abstract: A display device includes a display device including a substrate, and a display unit disposed on the substrate. An encapsulating unit encapsulates the display unit. The encapsulating unit includes a barrier organic layer. The barrier organic layer includes a plurality of organic materials and a plurality of inorganic materials. The inorganic materials are arranged in free volumes between the organic materials.

Abstract: An insulated gate semiconductor device includes p+ gate bottom protection regions embedded in a drift layer at the bottoms of trenches that goes through n+ source regions and p-type base regions, and p+ base bottom embedded regions embedded in the drift layer below the base regions. The base bottom embedded regions have trapezoidal shapes due to a channeling phenomenon, and the bottom surfaces of the base bottom embedded regions are deeper than the bottom surfaces of the gate bottom protection regions.

Abstract: Apparatus and method for monitoring wafer charges are proposed. A conductive pin, a conductive spring and a conductive line are configured in series to connect the backside surface of the wafer and the sample conductor so that the backside surface of the wafer and the surface of the sample conductor have identical charge density. Hence, by using a static electricity sensor positioned close to the surface of the sample conductor, the charges on the wafer may be monitored. Note that the charges appeared on the frontside surface of the wafer induces charges on the backside surface of the wafer. As usual, the sample conductor is a sheet conductor and properly insulated from the surrounding environment. As usual, the sample conductor and the static electricity sensor are positioned outside the chamber where the wafer is placed and processed, so as to simplify the apparatus inside the chamber and reduce the contamination risk.

Abstract: An organic EL device includes a pair of electrodes and an organic compound layer between pair of electrodes. The organic compound layer includes an emitting layer including a first material, a second material and a third material, in which singlet energy EgS(H) of the first material, singlet energy EgS(H2) of the second material, and singlet energy EgS(D) of the third material satisfy a specific relationship.

Abstract: A method for forming a semiconductor device and semiconductor device is disclosed. In one example, the method includes forming a silicone layer on a semiconductor die. The method further includes plasma treating a silicone surface of the silicone layer. A surfactant is deposited on the plasma-treated silicone surface of the silicone layer to obtain a silicone surface at least partly covered by surfactant. A mold is formed on the silicone surface at least partly covered by surfactant. The surfactant includes surfactant molecules comprising an inorganic skeleton terminated by organic compounds.

Abstract: Provided herein are charge generating devices and methods of making and use thereof. The charge generating devices comprise a substrate having a top surface; a plurality of spaced-apart three-dimensional elements disposed on the top surface of the substrate; and a plurality of cavities formed by the plurality of spaced-apart three-dimensional elements, the plurality of cavities being the area between the plurality of spaced-apart three-dimensional elements. The charge generating devices can further comprise a radioactive layer disposed on at least a portion of the plurality of spaced-apart three-dimensional elements and the top surface such that the plurality of cavities and the top surface are substantially coated by the radioactive layer. In some examples, the charge generating devices can comprise a radiation material and/or a scintillating material disposed within at least a portion of the plurality of cavities.

Abstract: A semiconductor light emitting device including a first conductive electrode and a second conductive electrode; a first conductive semiconductor layer on which the first conductive electrode is disposed; a second conductive semiconductor layer overlapping the first conductive semiconductor layer, on which the second conductive electrode is disposed; and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer. Further, the second conductive semiconductor layer includes a first layer including a porous material capable of being electro-polished and disposed on an outer surface of the semiconductor light emitting device; a second layer disposed under the first layer and having a lower impurity concentration than the first layer; and a third layer disposed between the second layer and the active layer and having a higher impurity concentration than the second layer.

Abstract: A semiconductor device includes a base element and a copper element over the base element. The copper element includes a layer stack having at least two copper layers and at least one intermediate conductive layer of a material different from copper. The at least two copper layers and the at least one intermediate conductive layer are alternately stacked over each other.

Abstract: Integrated active-matrix light emitting pixel arrays based displays and methods of fabricating the integrated displays are provided. An example method includes: forming multiple layers on a first substrate to form a light emitting structure, integrating the light emitting structure on the first substrate with a backplane device on a second substrate by connecting a first top layer of the light emitting structure with a second top layer of the backplane device, e.g., by using low temperature bonding, the backplane device including at least one backplane having pixel circuits, and after the integration, patterning the light emitting structure to form an array of light emitting elements each conductively coupled to respective pixel circuits to thereby form an array of active-matrix light emitting pixels. A pattern of different color phosphor or different size quantum dots materials can be deposited on the light emitting pixels to form an array of multi-color display pixels.

Abstract: An optical member for a multi-panel display device according to an embodiment includes a first optical member located on a first display device and including optical fibers, a second optical member located on a second display device neighboring the first display device and including optical fibers, and an optical fiber triangular bar located to overlap a region where the first and second optical members are adjacent to each other, and including optical fibers, wherein each of the first and second optical members includes a chamfer portion corresponding to the optical fiber triangular bar at the region where the first and second optical members are adjacent to each other.

Abstract: An electrical package may comprise a first substrate with a first substrate surface, and a microprocessor chip connected to the first substrate surface. The microprocessor chip may comprise a first chip surface that electrically connects to the first substrate surface, and a second chip surface located opposite the first chip surface. The electrical package may comprise a heat spreader assembly that comprises a lid section and a contact surface thermally connected to the second-chip surface. The electrical package may also comprise a pedestal between the contact surface and the lid section. The pedestal may comprise a first end that is located near the contact surface and a second end that is located near the lid section. The second end may be wider than the first end.

Abstract: This disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The semiconductor device may include a substrate; a first fin on the substrate for forming a first electronic component; a first gate structure on a portion of the first fin including a first gate dielectric layer on a portion of the first fin and a first gate on the first gate dielectric layer; and a first source region and a first drain region that each at one of two sides of the first gate structure and at least partially located in the first fin, where the first gate dielectric layer comprises a first region abutting against the first drain region, a second region abutting against the first source region, and a third region between the first region and the second region, and wherein thickness of the first region is greater than that of the third region.