Abstract: A redundant array includes a plurality of disks, a bus coupling the disks, a receiving device, and a device to reconstruct a block stored in one of the disks. The device reconstructs the block with associated data and parity blocks from other disks. The device transmits the reconstructed block to the receiving device in response to the one of the disks being unavailable or degraded.

Abstract: A method and apparatus is described for remote monitoring of digital processing systems. A remote monitoring digital processing system may be connected to one or more digital processing systems to be monitored. A diagnostic program may be executed on the remote monitoring digital processing system to generate diagnostic information relating to each monitored digital processing system.

Abstract: A method of debugging using a USB connecting system. A debug signal function is installed in the BIOS of a target PC, and a host PC is provided with monitor software. A USB interface is used to connect the target PC and the host PC, using the host PC to monitor the debugging state of the BIOS of the target PC. The invention thus achieves the goal of debugging a system through a USB.

Abstract: Devices and methods for processing data transmission units (DTUs) that are either entering or exiting a network. A device having multiple processor modules is provided along with a controller and an interface for the multiple processors. Each processor can work on any one of the connection levels and can independently process incoming or outgoing DTUS. Each processor module can perform the required calculations and data manipulation required for BIP 8 calculation, binning, and trail trace identifier validation. The controller receives the incoming or outgoing DTUS and assigns these DTUS to the appropriate processor module that is working on that connection. Connections can be added or dropped as required by the controller which also handles the assignment of the processor modules to the connections. Furthermore, also provided is an offset scheme for the numbering of the connection levels that avoids a zero connection level that may arise due to an AIS event.

Abstract: A device for analyzing digital data formulated in accordance with a communication protocol has a data memory for storing digital data to be analyzed. A microcode memory stores a microcode that represents at least part of the communication protocol. A data register is loaded with a pre-determined number of bits from the data memory, and a microcode register is loaded with a pre-determined number of bits from the microcode memory. The content of the microcode register is used to analyze the content of the data register. The results of the analysis are stored in an output memory. An addressing unit for the data memory and another addressing unit for the microcode memory take into account the contents of the data and/or microcode registers in determining the corresponding addresses.

Abstract: A method and system for promoting fault tolerance in a multi-node computing system that provides deadlock-free message routing in the presence of node and/or link faults using only two rounds and, thus, requiring only two virtual channels to ensure deadlock freedom. A lamb set of nodes for use in message routing is introduced, with each node in the lamb set being used only as points along message routes, and not for sending or receiving messages.

Abstract: A network node, a system and method for facilitating safety in a communication network of a safety-related system, involving the means to accomplish the steps of receiving at a network note at least one packet, forming a relative measure of data corruption, and initiating a failsafe reaction when said relative measure of data corruption exceeds specifiable safety parameters.

Abstract: A system and method for testing a group of related products or devices. According to one embodiment, the user may first manually create a base test sequence, and child test sequences may then be created based on the base test sequence. The user may include various steps in the base test sequence, such that the base test sequence includes steps that need to be common to most or all of the child test sequences. The user may also configure parameters or properties for each step in the base test sequence, such that the parameter configuration is what is required for most or all of the child test sequences. Initial child test sequences may then be automatically created as instances of the base test sequence. The user may then manually edit the instances of the base test sequence to produce the desired child test sequences, such that each child test sequence is configured to appropriately test a particular product to which the child test sequence corresponds.

Abstract: The present invention provides a method, computer program product, input/output device, and computer system for stress testing the I/O subsystem of a computer system. An input/output device capable of engaging in repetitive direct memory access (DMA) transfers with pseudo-randomized transfer parameters is allowed to execute multiple DMA transfers with varying parameters. In this way, a single type of device may be used to simulate the effects of multiple types of devices. Multiple copies of the same I/O device may be used concurrently in a single computer system along with processor software to access the same portions of memory. In this way, false sharing, true sharing may be effected.

Abstract: A wireless diagnostic system for diagnosing a problem with at least one server includes a portable diagnostic tool. The portable diagnostic tool includes a wireless transmitter and a wireless receiver. The portable diagnostic tool is configured to transmit requests with the tool's wireless transmitter. A wireless communication subsystem is coupled to a first server. The wireless communication subsystem includes a wireless transmitter and a wireless receiver. The wireless communication subsystem is configured to receive a transmitted request from the portable diagnostic tool with the subsystem's wireless receiver. The wireless communication subsystem is configured to transmit service information with the subsystem's wireless transmitter in response to a received request. The portable diagnostic tool is configured to receive the service information with the tool's wireless receiver.

Abstract: Smooth release of resources on a switch node adapter to a diagnostics program is provided without requiring rebooting of the system. The release technique includes: setting a first flag at a device driver associated with the adapter to block new open system calls from opening the device driver; broadcasting an adapter down event to instruct internet protocol (IP), fault service daemon (FSD) and application program interface (API) components of the node to release resources on the adapter; and setting a second flag at the device driver to block input/output control calls other than from the diagnostics program. When the device driver supports multiple adapters, only the adapter undergoing diagnostics is suspended, the remaining adapters remain up to components of the switch node. Upon completion of diagnostics, components remaining in open state are restarted on their communication windows at the adapter.

Abstract: An integrated circuit, a client computer system, and a method for using a watchdog timer as a check before changing the system state of a computer system. The integrated circuit includes a first bus interface logic for coupling to a first external bus, a watchdog timer, and logic configured to receive a request for a system reset. The watchdog timer is coupled to receive a reset input upon a predetermined change in a system state. The watchdog timer is further configured to provide an indication in response to an expiration of the watchdog timer. The logic is configured to query the watchdog timer for the expiration of the watchdog timer in response to receiving the request for the system reset.

Abstract: A remote controller is coupled to a target system via a computer network A real time probe is installed in software executing on a target system, typically a Digital Signal Processor (DSP). The remote controller includes a “debugger user interface” which accepts and interprets scoping commands issued by a developer. A controller network driver constructs appropriate network packets to be sent over the network to the target system. The target system has a control processor which runs a target network driver for receiving the network packets containing the scoping commands. The scoping commands are sent to an “embedded debugger” which performs the requested probing/scoping. When the DSP code runs across an address where the probe is installed, the embedded debugger will collect the signal values. The collected scope data will be interleaved and sent to the target network driver which, will encapsulate the information into suitable packets to send back to the controller via the network.

Abstract: Methods of automatically generating trouble tickets for network elements which are in failure and affecting network performance. The network elements are sectionalized into their basic components so that the failure in the elements can be localized and diagnosed. Once the failure has been diagnosed, a trouble ticket is automatically generated my network maintenance so that the repair of the element can be scheduled and undertaken. The trouble tickets are made available via the network to customers that are concerned that circuits on which they operate and which may be malfunctioning due to the network element failure can be kept informed of the status of the repair and the failure.

Abstract: In the memory management method, when a failure is detected in the power supplied to a protective memory, a control toward the memory is cut off from a CPU and the power supply is switched to a standby power before the protective memory has some damaging effect; after solution of the power failure, the switching is finished, the control toward the memory is returned to the CPU, and the power supply is returned to an ordinal one; write completion of data is notified to the client at a time when the data sent from the client has been written into the protective memory; whether the last termination is abnormal or normal is checked at the activation; when the last termination is abnormal, the protective memory is returned after memories other than the protective memory are initialized at the activation; and when the last termination is normal, the protective memory is returned and thereafter all the memories are initialized at the activation.

Abstract: RAID information and physical position information of hard disk units are managed by a disk controller in a mapped fashion. When the physical position of the hard disk units is changed, the information mapping is retried. Further, the positional information of the hard disk units accommodated in a disk array system under the administration of the disk controller, is calculated so as to form n-dimensional coordinate system information, and the resulting information is stored in each of the hard disk units. When the hard disk units are inserted into the disk array system, the n-dimensional coordinate system information is read from each hard disk unit. If it is detected that there is difference from the current coordinate system information, then information before removal and that after the insertion are compared with each other and a data link is reconstructed.

Abstract: An OR circuit (34, 35) OR-operates an emulator reset signal (106, 107) based on a reset instruction from an emulator (30) and an external reset signal (115, 116) supplied from an external reset generation circuit. The OR operation result is distributed and supplied to a processor (10) and a companion chip (20) as a system reset signal (109, 110), thereby initializing both chips of the processor (10) and the companion chip (20) in accordance with the reset the emulator (30).

Abstract: A system includes a plurality of inter-connected servers coupled to a storage device. The servers are programmed so that one server functions as a primary and another server(s) functions as a backup slave server. When the slave detects that the primary has failed, the slave performs a number of actions to take over run-time operation for the primary. Each server includes a mass storage device controller and executable code that permits the slave to detect the primary's failure and take over for the primary. Such code is included in the mass storage device controller, not in the system ROM as in conventional systems. Because the system ROM is not burdened with code that is specific to the mass storage device controller, the system ROM need not be upgraded and reflashed each time a new mass storage device controller is inserted into the slave computer.

Abstract: A dynamic test generation method and apparatus enabling verification of the parallel instruction execution capabilities of VLIW processor systems is described. The test generator includes a user preference queue, a rules table, plurality of resource-related data structures, an instruction packer, and an instruction generator and simulator. The present invention generates a test by selecting instructions for parallel execution based upon resource availability as indicated by the resource-related data structures and the processor's instruction grouping rules, simulating the parallel execution of the instructions on a golden model, updating the resource-related data structures, and evaluating the updated architectural state of the golden model.

Abstract: A method and a device for reading and for checking the time position of a data response read out from a memory module to be tested, in particular a DRAM memory operating in DDR operation. In a test receiver, the data response from the memory module to be tested is latched into a data latch with a data strobe response signal that has been delayed. A symmetrical clock signal is generated as a calibration signal. The calibration signal is used to calibrate the time position of the delayed data strobe response signal with respect to the data response. The delayed data strobe response signal is used for latching the data response. The delay time is programmed into a delay device during the calibration operation and also supplies a measure for testing precise time relationships between the data strobe response signal (DQS) and the data response.