Abstract: A system and method of using of diagnostic procedures through a firmware interface in a processing system are described. A first physical area of a memory may store one or more diagnostic modules comprising machine-readable instructions for performing one or more diagnostic procedures of a processing system. A second physical area of the memory may store an operating system capable of initiating execution of the one or more diagnostic procedures through the firmware interface.

Abstract: A remote system fault detecting unit detects a fault in a remote system. A virtual resource management unit selects a virtual resource necessary for structuring a virtual system having the same system configuration as the remote system in which the fault has been detected, based on the remote system configuration information of the remote system. A virtual system structure unit structures a virtual system by using the selected virtual resource. A virtual system start unit starts the virtual system structured by the virtual system structure unit. When the fault in the remote system has been recovered, a virtual system stop unit stops the virtual system and the virtual resource management unit releases the virtual resource.

Abstract: A simultaneous and redundantly threaded, pipelined processor executes the same set of instructions simultaneously as two separate threads to provide fault tolerance. One thread is processed ahead of the other thread so that the instructions in one thread are processed through the processor's pipeline ahead of the corresponding instructions from the other thread. The thread, whose instructions are processed earlier, places its committed stores in a store queue. Subsequently, the second thread places its committed stores in the store queue. A compare circuit periodically scans the store queue for matching store instructions. If otherwise matching store instructions differ in any way (address or data), then a fault has occurred in the processing and the compare circuits initiates fault recovery. If comparison of the two instructions reveals they are identical, the compare circuit allows only a single store instruction to pass to the data cache or the system main memory.

Abstract: A headless computer entity having a plurality of disk drives operates to self restore to a known state, upon failure of either a system disk drive containing an operating system of the computer entity, or failure of a data disk drive containing application data. Depending upon whether the system disk and/or the data disk are replaced by a replacement disk, the computer entity configures itself with either deletion of application data on the data disk, or with deletion of application data on both the system disk and the data disk. The computer entity determines whether a new replacement disk has been installed by comparing a signature of the system disk with a signature of the data disk. If a replacement disk is detected, then the digital signatures are set by the computer entity such that the system disk and data disk have a self consistent set of hardware specific digital signatures. Application data is returned to a known good state after deletion.

Abstract: A fault monitoring system comprises a fault detection mechanism to determine the status of a parameter to be monitored. An integrator counts in one direction when a fault in the measurement system is detected and counts in an opposite direction in the absence of fault detection. A threshold detector generates a hard fault indication when the integrator count reaches a threshold value, and an integrator count monitor generates information indicative of the state of the integrator count when below the threshold value thereby providing an indication of the progression of the fault.

Abstract: A trace control circuit includes a branch event generation circuit 1 having an address abbreviation information generation circuit 8 for detecting a portion in which a branch-source address and a branch-destination address are overlapped with each other from the upper-bit side of the address data thereof and generating branch-destination address abbreviation information on the basis of the result of the detection, and a trace data abbreviation circuit 5 for performing abbreviation of one part of trace data in accordance with the branch-destination address abbreviation information and outputting the partly abbreviated trace data, whereby the number of data packets of the trace data can be reduced to speed up the output operation of the trace data, and the ability to output trace data in real time can be thereby improved greatly.

Abstract: The present invention relates to an apparatus for controlling safety-critical processes. The apparatus includes at least one safe control unit for controlling the safety-critical processes and at least two safe signal units which are connected via I/O channels to the safety-critical processes. The safe control unit and the safe signal units are connected to a common fieldbus. The safe signal units communicate with the safe control unit, but not with one another, when the apparatus is in the control mode. The safe signal units have an evaluator for evaluating a fault message which is broadcasted across the fieldbus, as well as a switching device which autonomously change the safety-critical process to a safe state when a fault message which is evaluated as being relevant occurs.

Abstract: A method for monitoring faults within a computer network. In a preferred embodiment, an event, a host, and a fault monitoring point triplet are received from a monitored network device. A database of valid fault monitoring points is consulted to determine the validity of the event, host, and fault monitoring point triplet received. Responsive to a determination that the event, host, and fault monitoring point triplet received are valid, the appropriate party to notify and the appropriate message to send are determined. The appropriate party is then sent a message alerting them to the network problem. Different parties may be notified depending on the nature of the event or on the location of the event. Furthermore, a new network device may be added without taking down the fault monitoring system by merely adding to the database of valid fault monitoring points a new fault monitoring point corresponding to the added network device.

Abstract: An improved method and system for detecting differences between first and second test executive sequence files in a computer system. Each of the test executive sequence files may comprise a plurality of interrelated objects. The objects may be compared and differences between the objects may be displayed. The objects may comprise one or more of: a sequence; a global variable; and/or a data type. A sequence may comprise: a step, a parameter, and/or a local variable. A step of a sequence may comprise a tree structure of step properties. Each step property may comprise one or more of: a property value, property flags, and/or a property comment. An object may comprise a hierarchy of objects (e.g., a parent object and a child sub-object). Differences between the hierarchy of objects may be detected. Differences may be navigated. Each displayed difference may be characterized as an insertion or a deletion.

Abstract: A simultaneous and redundantly threaded, pipelined processor executes the same set of instructions simultaneously as two separate threads to provide fault tolerance. One thread is processed ahead of the other thread so that the instructions in one thread are processed through the processor's pipeline ahead of the corresponding instructions from the other thread. The thread, whose instructions are processed earlier, places its uncached reads in a read queue. Subsequently, the second thread places its uncached reads in the read queue. A compare circuit periodically scans the read queue for matching uncached read instructions. If otherwise matching instructions differ in their target address, then a fault has occurred in the processing and the compare circuits initiates fault recovery. If comparison of the two instructions reveals they are identical, the compare circuit allows only a single uncached read instruction to pass to the system main memory.

Abstract: Processor modules (2) are supported side-by-side with one another to slide in and out of a cabinet (1) on tracks (6, 7), each module (2) including a PC-CPU motherboard (11) and a hard-disk unit (16) mounted on a metal plate (3). Power is supplied to all the modules (2) in parallel from two power-supply units (18) mounted in the back of the cabinet (1), each comprising a pair of power-supply modules (19). The pairs of power-supply modules (19) supply power in parallel with one another to the processor modules (2). Diode circuitry (20) is included in each power-supply module (19) to isolate that power-supply module (19) from its paired power-supply module (19) in the event that a fault occurs by which the output voltage of the respective power-supply module (19) fall below that of the power-supply module (19) with which it is paired.

Abstract: A method and a test tool 110 are provided for verifying the functionality of a software based unit 100 which is provided with an interface 105 for its external communication. Pre-recorded data is used for the reproduction of a test case and for the verification of a unit subject to the test case. The pre-recorded data includes pre-recorded input data 125 and pre-recorded output data 126. The pre-recorded input data is applied to an interface of the unit and the pre-recorded output data is compared with the data transmitted from the unit in response to the applied pre-recorded input data. If the data transmitted from the unit is in correspondence with the pre-recorded output data, the functionality of the unit in accordance with the specific test case has been verified.

Abstract: Systems and methodologies for use in signal measurement systems that acquire and store signal data in accordance with a trigger specification. In particular, the present invention is directed to a hardware resource allocator that is interposed between the signal acquisition hardware of a logic analyzer and the user interface on which a signal measurement specification model is presented to the operator. The hardware resource allocator translates the measurement requirements as specified by the user on the user interface to commands for allocation and control of the appropriate combination of hardware resources. Generally, the hardware resource allocator allocates and configures the requisite hardware resources and translates the measurement specification to hardware control data used by software drivers to program the signal acquisition hardware resources.

Abstract: A system and technique restarts a data plane of an intermediate node, such as an aggregation router, of a computer network without changing the state of a control plane in the router. The aggregation router comprises a control plane that includes a supervisor processor configured to manage traffic forwarding operations of the node. To that end, the supervisor processor maintains a current state of the control plane pertaining to, e.g., routing protocols and interface states of line cards within the router. The aggregation router further comprises a data plane that includes hardware components, such as a forwarding engine, configured to perform forwarding operations for data forwarded by the router.

Abstract: A real time, computerized, method, system, and method of doing business with respect to troubleshooting and resolving installed base product failures. A client establishes a link with the business server, filing a report describing the product and failure mode in plain text. The server compares the failure mode plain text to a historical data base, associating maintained keywords likely to appear in the report to product subunits associated with failure modes. Based on the comparison, the server calculates and transmits to the client predictions of resolving the failure. The client is provided with on-line capability for selecting and ordering replacements. The process is continuous, iterative, and interactive.

Abstract: A method and computer program product for performing error control of video bitstream data encoded according to a data partition technique used in communication through a wireless channel. The method includes the steps of (a) partitioning video bitstream data into units of information items having certain characteristics and encoding the video bitstream data, (b) calculating a checksum for controlling errors in each partitioned unit of the encoded video bitstream data, (c) constituting a packet, in which each checksum calculated in a the step (b) is added to the encoded video bitstream data and transmitting the packet through a wireless communication channel, and (d) receiving the packet transmitted in the step (c) and checking whether there is an error in each partitioned unit of the encoded video bitstream data through the checksum of each partitioned unit of the encoded video bitstream data.

Abstract: The invention provides a restart mechanism within a data processing system for restarts following a failure. The mechanism is provided in persistent storage as a recovery log containing recovery log records which can be used during recovery from the failure of the data processing system. The log records relate to units of work undertaken by the data processing system, and the mechanism retrieves, from the recovery log, a recovery log record relating to a unit of work, determines whether or not the unit of work meets at least one predetermined criterion, and performs a recovery process if the unit of work meets the predetermined criterion.

Abstract: This invention provides a tool for reliability evaluation and performance analysis of an IP backbone network by using the network packet loss ratio as the main measurement. A queuing model and algorithm is presented for calculating packet loss at congested interfaces or links. A reliability model is presented for considering network hardware component failures such as router failures, ATM switch failures, and physical link failures. Based on the measurement and models presented, a network reliability and performance (NetRAP) apparatus calculates IP network reliability and performance measurements. The NetRAP apparatus uses the network topology, a traffic matrix, and the reliability parameters of a network as inputs and calculates the network packet loss ratio and sigma score, and provides a list of heavily congested links under non-failure or different single failure conditions.

Abstract: Provided is a method, system, program, and data structure for deriving state information concerning a monitored system component. A status object is provided including information on a current state of the monitored system component. There are a plurality of states associated with the monitored system component, wherein each state is capable of having a state action and at least one transition condition associated with a transition state. A measured system parameter is received and a determination is made as to whether the received measured system parameter satisfies one transition condition associated with the current state indicated in the status object. If the received system parameter satisfies one transition condition, then the state action associated with the transition state associated with the satisfied transition condition is performed. The current state is set to the transition state in the status object.

Abstract: A CD-ROM decoder that performs code error correction and/or code error detection on digital data partitioned in sectors having a certain format includes a circuit for reading and analyzing the header information stored with each sector of CD-ROM data, which relieves a control microprocessor of having to perform such task. A header information register stores the header information for each sector of data. A sector information conversion circuit connected to the header information register determines the specific format of the sector data and generates corresponding sector information. The sector data and the corresponding sector information are stored in a buffer memory.