Patents Examined by B. Everhart
  • Patent number: 5350492
    Abstract: A method is disclosed for removing oxide from the surface of a semiconductor body having a thick oxide and an adjoining nitride-covered thin oxide, without subjecting the surface to significant over-etching and thus avoiding degredation of the surface of the semiconductor body. The thick oxide is first etched for a period of time so that a portion of the thick oxide remains, and has a thickness comparable to that of the thin oxide. The nitride covering the thin oxide is next removed without appreciably etching either the remaining portion of the thick oxide or the thin oxide. Finally, the thin oxide and the remaining portion of the thick oxide are removed, without appreciably over-etching the surface of the semiconductor body.
    Type: Grant
    Filed: September 18, 1992
    Date of Patent: September 27, 1994
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Steven C. Hall, Mark I. Gardner, Henry J. Fulford, Jr.
  • Patent number: 5346853
    Abstract: Substrate temperatures are maintained above 400.degree. C. During the microwave energized glow discharge deposition of Group IV semiconductor materials. The substrate temperature range provides for the preparation of materials having improved electrical properties. Cell efficiency of a photovoltaic device of the p-i-n type is significantly improved by depositing the intrinsic layer using a microwave generated plasma and a substrate temperature in excess of 400.degree. C. Maximum cell efficiency occurs for depositions carried out in the range of 400.degree.-500.degree. C.
    Type: Grant
    Filed: January 21, 1994
    Date of Patent: September 13, 1994
    Assignee: United Solar Systems Corporation
    Inventors: Subhendu Guha, Chi C. Yang, XiXiang Xu
  • Patent number: 5336363
    Abstract: Copper lines can be formed on a semiconductor wafer at low temperatures by forming a patterned photoresist layer over a copper layer, and etching the copper in a vacuum etch chamber using vaporized acetic acid and water as the etchants.
    Type: Grant
    Filed: September 24, 1993
    Date of Patent: August 9, 1994
    Assignee: Applied Materials, Inc.
    Inventor: Katsumi Morita
  • Patent number: 5336371
    Abstract: In a wafer fabrication process in which a photoresist stripper must be removed from the surface of a semiconductor wafer, the photoresist stripper is rinsed by inserting the wafer in a vessel (23, FIG. 3) filled with water and simultaneously pumping carbon dioxide and water into the vessel to cause the water to overflow the vessel. Preferably, the wafer is contained within the vessel for at least five minutes, and, during the rinsing step, the water completely fills the vessel and overflows at a rate of at least fifty percent of the volume of the vessel each minute. We have found that this method of rinsing photoresist stripper from semiconductor wafers significantly reduces or eliminates the incidence of corrosion pitting on aluminum conductors (12, FIG. 1) of the wafer (11).
    Type: Grant
    Filed: March 18, 1993
    Date of Patent: August 9, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Bryan C. Chung, Gerald N. DiBello, Charles W. Pearce, Kevin P. Yanders
  • Patent number: 5334539
    Abstract: Acetylene containing poly(p-phenyleneacetylene) (PPA) - based light-emitting diodes (LEDs) are provided. The LEDs are fabricated by coating a hole-injecting electrode, preferably an indium tin oxide (ITO) coated glass substrate, with a PPA polymer, such as a 2,5-dibutoxy or a 2,5-dihexoxy derivative of PPA, dissolved in an organic solvent. This is then followed by evaporating a layer of material capable of injecting electrons, such as A1 or A1/Ca, onto the polymer to form a base electrode. This composition is then annealed to form efficient EL diodes.
    Type: Grant
    Filed: January 29, 1993
    Date of Patent: August 2, 1994
    Assignee: Iowa State University Research Foundation, Inc.
    Inventors: Joseph Shinar, Leland S. Swanson, Feng Lu, Yiwei Ding
  • Patent number: 5334555
    Abstract: A silicon nitride film is deposited on a semiconductor substrate in a plasma generated with SiH.sub.4 and nitride gases by the application of high-frequency electric energy. An allowable range of ultraviolet radiation absorption rates of the silicon nitride film, and also an allowable range of inner stresses of the silicon nitride film are established. Levels of both the flow rate of the SiH.sub.4 gas and the high-frequency electric energy are determined so that the silicon nitride film will satisfy the allowable range of ultraviolet radiation absorption rates with a wide margin and the allowable range of inner stresses with a wide margin.
    Type: Grant
    Filed: November 6, 1992
    Date of Patent: August 2, 1994
    Assignee: Sony Corporation
    Inventors: Toshinobu Sugiyama, Hiroshi Sakurai
  • Patent number: 5332468
    Abstract: Method for structuring a layer. For structuring a layer that is arranged on a lower layer of a different material using a plasma etching process, a target (14) of the material of the lower layer is arranged in an etching reactor (1). The etching process is managed such that material is sputtered from the target (14) and is deposited on surfaces of the lower layer exposed in the etching process to essentially the same degree to which the lower layer is eroded by the etching process. The method is particularly suited for structuring a polysilicon layer that is arranged on a gate oxide layer.
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: July 26, 1994
    Assignee: Siemens Aktiengesellschaft
    Inventor: Manfred Engelhardt
  • Patent number: 5332441
    Abstract: Apparatus for plasma processing involving the gettering of particles having a high charge to mass ratio away from a semiconductor wafer are disclosed. In one aspect of the invention, magnets are used to produce a magnetic field which is transverse to an electric field to draw the negative particles away from the wafer to prevent the formation of a sheath which can trap the particles. In a second aspect of the invention, a power source is connected to the wafer electrode to maintain a negative charge on the wafer, thereby preventing negative particles from being drawn to the wafer surface when the plasma is turned off. In other embodiments of the invention, a low density plasma source is used to produce a large plasma sheath which permits particles to cross a chamber to be gettered. A low density plasma discharge followed by a pulse to a higher density is used to overcome the negative effect of an insulating layer between the wafer and the wafer electrode.
    Type: Grant
    Filed: October 31, 1991
    Date of Patent: July 26, 1994
    Assignee: International Business Machines Corporation
    Inventors: Michael S. Barnes, Dennis K. Coultas, John C. Forster, John H. Keller, James A. O'Neill
  • Patent number: 5330936
    Abstract: A method of producing a silicon nitride film free of photolithographty and dry etching processes and a method of fabricating a semiconductor memory cell device are disclosed. A first polycrystalline silicon film serving as a bottom electrode is selectively formed only on a silicon region of the substrate with a field oxide film and a silicon nitride film is selectively formed only on the first polycrystalline silicon film by selective chemical vapor deposition in which a source gas including a combination of both ammonia and either silane or dichlorosilane is doped with hydrogen chloride. Then, a second polycrystalline film serving as a top electrode is selectively formed on the silicon nitride film.
    Type: Grant
    Filed: May 27, 1992
    Date of Patent: July 19, 1994
    Assignee: NEC Corporation
    Inventor: Akihiko Ishitani
  • Patent number: 5326490
    Abstract: Sulfuric acid or sulfuric acid/hydrogen peroxide cleaning solutions used in semiconductor manufacturing processes are improved in wettability and cleaning effect by lowering their surface tension through the addition of surface-active agents Of the general formula R.sup.1 SO.sub.2 NR.sup.2 C.sub.2 H.sub.4 OA(I) wherein R.sup.1 stands for a fluoroalkyl group, R.sup.2 for H or a lower alkyl group and A for H or SO.sub.3 H.
    Type: Grant
    Filed: November 15, 1990
    Date of Patent: July 5, 1994
    Assignees: Kanto Kagaku Kabushiki Kaisha, Nissan Chemical Industries, Ltd.
    Inventors: Kiyoto Mori, Takao Shihoya, Hisao Hara, deceased
  • Patent number: 5326427
    Abstract: A method of selectively etching titanium-containing materials without attacking aluminum or silicon dioxide is describe, wherein an atomic chlorine etching environment is generated using downstream techniques. Atomic chlorine in the absence of ion bombardment (as provided by downstream etching) etches titanium-containing materials such as titanium nitride without attacking silicon dioxide. In one embodiment of the invention, atomic chlorine is generated by the discharge of energy into molecular chlorine. In another embodiment of the invention, discharge of energy into a fluorine-containing gas causes the generation of atomic fluorine. Molecular chlorine is then added, creating a fluorine-chlorine exchange reaction which produces atomic chlorine. The presence of fluorine inhibits etching of aluminum, but does not impede the etching of titanium-containing materials.
    Type: Grant
    Filed: September 11, 1992
    Date of Patent: July 5, 1994
    Assignee: LSI Logic Corporation
    Inventor: Chris Jerbic
  • Patent number: 5322806
    Abstract: A method of producing a semiconductor device including the steps of depositing a refractory metal gate electrode at a predetermined region of a semi-insulating substrate surface, and thereafter depositing an insulating film at regions other than the gate electrode region, wherein the production of the insulating film is carried out by an electron cyclotron resonance plasma CVD method while applying a high frequency electrical bias to the substrate.
    Type: Grant
    Filed: August 15, 1989
    Date of Patent: June 21, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasutaka Kohno, Masayuki Sakai
  • Patent number: 5320984
    Abstract: There is disclosed a method for forming a semiconductor film having a high electrical conductivity on a substrate at a low temperature below 200.degree. C. with high productivity by sputtering. For example, the sputtering process is carried out within an inert atmosphere consisting of an inert gas such as argon and hydrogen. The substrate is electrically insulated (floating) from the surroundings. The distance between the substrate and a target is set to a large value. Preferably, the ratio of the partial pressure of the hydrogen to the total pressure is 30 % or more. The target consists of a semiconductor doped with an impurity that imparts one conductivity type to the semiconductor, in the case where a semiconductor film containing an impurity that imparts the conductivity type to the semiconductor film is formed on the substrate. This impurity is for example a group III or V element.
    Type: Grant
    Filed: December 20, 1991
    Date of Patent: June 14, 1994
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Shunpei Yamazaki, Takashi Inushima
  • Patent number: 5318928
    Abstract: The method calls for introducing an inert gas into a tank where a high frequency energy source is applied to internal electrodes for the ignition of a plasma within the tank. The sensor surface is cleaned by sputtering away impurities from the sensor surface by means of plasma particles striking the sensor surface. Next, a monomer containing silicon and a reactive gas are introduced into the tank with continuous throttling of the inert gas feed and maintenance of the plasma, while the electric power characteristics fed into the plasma are being controlled. This leads to the deposition on the sensor surface of a compound composed of particles from the monomer containing silicon and from the reactive gas.
    Type: Grant
    Filed: June 11, 1992
    Date of Patent: June 7, 1994
    Assignee: Leybold Aktiengesellschaft
    Inventors: Rainer Gegenwart, Jochen Ritter, Helmut Stoll, Norbert Weimer, Hans-Dieter Wurczinger
  • Patent number: 5316974
    Abstract: An improved metallized structure (10) is formed from a copper seed layer (46) and a copper structure (48). Semiconductor devices to be connected (16-18) are covered by a conductive barrier layer (20). An oxide layer (28) is then deposited over the barrier layer (20) and patterned using standard photolithographic techniques and an anisotropic plasma etch. Vertical sidewalls (36-38) are formed by the etch and an HF deglaze. A seed layer (44-46) is then sputtered onto a photoresist layer (30) and the exposed barrier layer (20). After stripping the photoresist (30) and the seed layer (44) thereon, the copper structure (48) is electroplated over the remaining seed layer (46). The structure (48) thus formed has approximately vertical sidewalls (24-26) for improved contact with subsequent layers.
    Type: Grant
    Filed: April 30, 1990
    Date of Patent: May 31, 1994
    Assignee: Texas Instruments Incorporated
    Inventor: Sue E. Crank
  • Patent number: 5314845
    Abstract: A two step process is disclosed for forming a silicon oxide layer over a stepped surface of a semiconductor wafer while inhibiting the formation of voids in the oxide layer which comprises depositing a layer of an oxide of silicon over a stepped surface of a semiconductor wafer in a CVD chamber by flowing into the chamber a gaseous mixture comprising a source of oxygen, a portion of which comprises O.sub.3, and tetraethylorthosilicate as the gaseous source of silicon while maintaining the pressure in the CVD chamber within a range of from about 250 Torr to about 760 Torr and then depositing a second layer of oxide over the first layer in a CVD chamber by flowing into the chamber a gaseous mixture comprising a source of oxygen, a portion of which comprises O.sub.3 ; and tetraethylorthosilicate as the gaseous source of silicon while maintaining the CVD chamber at a lower pressure than during the first deposition step.
    Type: Grant
    Filed: February 2, 1990
    Date of Patent: May 24, 1994
    Assignee: Applied Materials, Inc.
    Inventors: Peter W. Lee, David N. Wang, Makoto Nagashima, Kazuto Fukuma, Tatsuya Sato
  • Patent number: 5314848
    Abstract: Described is a method for manufacturing semiconductor devices which includes a heat treating process for heating and cooling semiconductor substrates mounted on a boat at a predetermined pitch according to a predetermined temperature profile, in order to flatten the surface of each semiconductor substrate by reflowing an insulating film containing impurities, for example, a BPSG film formed on the substrate. In the heat treating process, one of the control factors which affects the formation of grains or particles due to the impurities contained in the insulating film is set so as to prevent the impurities from generating grains or particles during the heat treatment. Also disclosed is a method of preventing the generation of grains or particles by widening the pitch of the mounted substrates.
    Type: Grant
    Filed: September 24, 1991
    Date of Patent: May 24, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takatoshi Yasui, Chiaki Kudo, Ichiro Nakao, Toyokazu Fujii, Yuka Terai, Shinichi Imai, Hiroshi Yamamoto, Yasushi Naito
  • Patent number: 5312781
    Abstract: A method for wet etching disposable spacers in silicon integrated circuits is provided. Illustratively, a pair of spacers is formed over a polysilicon substrate. A second pair of spacers is formed from doped silicon dioxide over the first pair of spacers. Then the second pair of spacers is etched away with NH.sub.4 OH/H.sub.2 O.sub.2, thus providing a means for defining the underlying polysilicon layer, e.g., by etching.
    Type: Grant
    Filed: November 12, 1991
    Date of Patent: May 17, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Richard W. Gregor, Chung W. Leung
  • Patent number: 5312778
    Abstract: A method for plasma processing characterized by the steps of disposing a wafer proximate to a cathode within a process chamber, releasing a gas into the chamber, applying R.F. power in the VHF/UHF frequency range to the cathode to form a plasma within the chamber, developing a magnetic field within the chamber having flux lines substantially perpendicular to the surface of the wafer, and varying the strength of the magnetic field until a desired cathode sheath voltage is attained. The apparatus includes a chamber, a wafer-supporting cathode disposed within the chamber, a mechanism for introducing gas into the chamber, an R.F.
    Type: Grant
    Filed: November 23, 1990
    Date of Patent: May 17, 1994
    Assignee: Applied Materials, Inc.
    Inventors: Kenneth S. Collins, Chan-Lon Yang, John M. White
  • Patent number: 5312783
    Abstract: A process for the preparation of a high dielectric thin film. A tantalum oxide film is formed on a substrate at a temperature of from 400.degree. to 850.degree. C. by means of an electron cyclotron resonance plasma chemical vapor deposition (ECR plasma CVD) method. A high dielectric film having little leakage current, good surface flatness and good step coverage is obtained.
    Type: Grant
    Filed: May 28, 1992
    Date of Patent: May 17, 1994
    Assignee: Fujitsu Limited
    Inventors: Kanetake Takasaki, Satoshi Nakai