Abstract: The glow discharge deposition of thin film materials is most advantageously carried out at a pressure which is less than the pressure of the minimum point on the deposition system's Paschen curve and at a power which is in excess of the minimum power required to sustain a deposition plasma at the particular process pressure.

Abstract: A method for fabricating a semiconductor device, which involves a technique for monitoring the temperature of the semiconductor substrate in which the device is formed, is disclosed. In accordance with the inventive technique, light, to which the substrate is substantially transparent, is impinged upon the substrate, and the intensity of either the reflected or transmitted light is monitored. If, for example, the intensity of the reflected light is monitored, then this intensity will be due to an interference between the light reflected from the upper surface of the semiconductor substrate and the light transmitted through the substrate and reflected upwardly from the lower surface of the substrate. If the temperature of the substrate varies, then the optical path length of the light within the substrate will vary, resulting in a change in the detected intensity.

Abstract: A method for manufacturing a semiconductor device with a Schottky electrode includes the steps of subjecting the surface of a GaAs substrate to a sputtering etching process in a sputtering processing chamber of a sputtering device; and depositing Schottky electrode material by sputtering on the surface of the substrate to form a Schottky electrode in the processing chamber without exposing the substrate to the atmosphere.

Abstract: Disclosed is a method of selective chemical vapor deposition for selectively forming thin films of a semiconductor, dielectric or metal on a semiconductor by providing a mask of SiO.sub.2 having a plurality of openings in various forms on the substrate, wherein a trimethyl gallium (TMG) gas as a Group III material, 10% hydrogen-based arsine (AsH.sub.3) gas as a Group V material, and 500 ppm hydrogen-based disilane (Si.sub.2 H.sub.6) gas as an n-type impurity material are alternately supplied onto the substrate, and each supply amount of the material gases is controlled at a value to obtain a film growth rate for forming the corresponding monoatomic layer or monomolecular layer to each material at each opening. Also disclosed is an apparatus for performing the above-disclosed method of chemical vapor deposition, wherein four reaction chambers are included, and the material gases are supplied to the respective reaction chambers in accordance with the following gas supply sequences: Chamber 1: TMG+H.sub.2 /H.

Abstract: A solid source chemical vapor deposition apparatus and a CVD method for fabricating semiconductor devices are disclosed. In accordance with the process for fabricating semiconductor devices, a CVD reactor chamber having a solid reactant source apparatus coupled thereto is provided. The reactant source apparatus includes a container which can be heated in a controllable manner and which has a gas diffuser located in the container. The container is provided with gas input and output which are located so that a carrier gas can be passed through the gas diffuser and through a finely divided solid reactant source material which is positioned over the gas diffuser. The carrier gas together with any vapor derived from the solid reactant source material is conveyed from the outlet of the reactant source apparatus to the CVD reactor chamber.

Abstract: An improved method of manufacturing a semiconductor device includes forming an insulating layer on a substrate, depositing a metal film layer on the insulating layer and depositing a photoresist layer on the metal film layer. The photoresist layer is formed with openings through which a predetermined surface of the metal film layer is exposed. The predetermined surface of the metal film layer is subjected to dry etching so that an underlying portion of the insulating layer is exposed. The remaining portion of the photoresist layer is then subjected to ashing by using an isopropyl alcohol-containing gas to expose the surface of said metal film layer.

Abstract: Phosphor-doped silicon films are simultaneously formed on semiconductor wafers, respectively. The semiconductor wafers are contained in a reaction tube whose interior temperature is controlled to 500.degree. C. Si.sub.2 H.sub.6 and PH.sub.3 are introduced into the reaction tube. PH.sub.3 is preheated to 400.degree. C. in a gas activating unit before being introduced into the reaction tube. By virtue of the preheating, the thermal decomposition of PH.sub.3 carried out in the reaction tube is accelerated.

Abstract: This invention relates to a semiconductor substrate having a porous surface nd to the amperometric receptor-based sensors formed with the substrate. More specifically, this invention pertains to the substrate in the form of a bipolar junction transistor having a porous hydrophilic surface directly on its base wherein the surface forms a support for an amperometric sensor. The invention also pertains to the methods of making and using the substrate and sensor.

Abstract: A gettering treatment process comprises the step of irradiating an ultraviolet light onto an insulating layer (a silicon oxide thin layer formed by thermally oxidizing silicon), in a chlorine-containing gas atmosphere. The ultraviolet light excites and dissociates the chlorine-containing gas thereby to generate chlorine radicals which uniformly penetrate the insulating layer, and serve to trap metal impurities within the silicon oxide thin layer.

Abstract: A plasma process apparatus capable of operation significantly above 13.56 MHz can produce reduced self-bias voltage of the powered electrode to enable softer processes that do not damage thin layers that are increasingly becoming common in high speed and high density integrated circuits. A nonconventional match network is used to enable elimination of reflections at these higher frequencies. Automatic control of match network components enables the rf frequency to be adjusted to ignite the plasma and then to operate at a variable frequency selected to minimize process time without significant damage to the integrated circuit.

Abstract: A passivation technique which significantly reduces degradation in reverse breakdown voltage characteristics usually introduced by passivation of active regions of field effect transistors is described. The technique uses a surface treatment in a plasma to introduce into the surface an electro-negative species to maintain negative surface potential of the surface subsequent to encapsulation by the passivation material.

Abstract: A method for producing polycrystalline semiconductor material layers of, in particular, silicon by vapor phase deposition in a plasma reactor. Hydrogen in its activated condition is supplied to the reaction gas in the reactor through an additional gas feed. In an embodiment, the activation proceeds with a glow cathode located in the hydrogen gas feed. The method enables the deposition of uniform polycrystalline semiconductor material layers at substrate temperatures of from between approximately 100.degree. to about 450.degree. C. The deposition can be implemented onto normal glass substrates in a plasma reactor having a simple structure. The method can be used for the manufacture of transistors through thin-film technology.

Abstract: A method using implantation to form a semiconductor laser or laser array with current blocking implants. A semiconductor material laser structure including layers of a first conductivity type, an active region and layers of a second conductivity type is formed. In a first embodiment, impurity ions of the second conductivity type are implanted into selected regions of a first conductivity type layer. The implanted ions form current blocking buried regions of the second conductivity type with current confining channels therebetween. Finally, the structure is thermally annealed. In a second embodiment, a disorder inducing impurity, which may be a saturable absorber, is diffused into selected portions of the layers of the first conductivity type through the active region. The diffusion converts side regions of those layers into the second conductivity type.

Abstract: A method for depositing a passivation layer on a semiconductor structure having a high resistance value polysilicon layer formed thereon while maintaining the high resistance value thereof and comprises sequentially depositing a silicon oxide layer and a silicon nitride layer, on a high resistance value polysilicon layer of a partially completed semiconductor structure to form a passivation layer thereover. The passivation layer including the silicon oxide layer and the silicon nitride layer is annealed with oxygen plasma in a chamber. The annealed passivation layer is then heated in the presence of a conditioning gas in the chamber to thereby maintaining the resistance of the high resistance value polysilicon layer.

Abstract: An apparatus and method for chemical vapor deposition in which the reactants directed toward a substrate to be provided with one or more films are first subjected to an electric field. The electric field is applied between two electrodes and the reactants become polarized in the field, thus stretching their polarized chemical bonds close to the breaking point. The apparatus also applies voltage pulses between one of the electrodes and the substrate. By adjusting the pulse height, pulse width and pulse repetition rates, the chemical bonds of polarized reactants break to produce free radicals and some ions of the desired elements or compounds. The substrate is kept at a given temperature. The free radicals react to deposit the desired film of high purity on the substrate. The deposition characteristics of the deposited films in terms of isotropic, anisotropic and selective deposition are controlled by the pulse height, width, repetition rates and by other process parameters.

Abstract: In an apparatus for the plasma treatment of semiconductor devices, a cover is provided on the outer periphery of the space between the upper and lower electrodes. By virtue of the provision of the cover on the outer periphery of the inter-electrode space, the processing gas ejected from ejection holes on one surface of the upper electrode diffuses evenly in the inter-electrode space to reach the surface of the semiconductor wafer. Therefore, it is possible to improve the efficiency at which the wafer is processed as well as the evenness with which various portions of the surface of the wafer are treated.

Abstract: A DRAM cell having a doped monocrystalline silicon substrate for the cell's lower capacitor plate whose surface has been texturized multiple times to enhance cell capacitance. After texturization, a thin silicon nitride layer is deposited on top of the texturized substrate, followed by the deposition of a poly layer, which functions as the cell's upper, or field, capacitor plate. The nitride layer, conformal and thin compared to the surface texture of the mono substrate, transfers the texture of the substrate to the cell plate layer. The effective capacitor plate area is substantially augmented, resulting in a cell capacitance increase of at least approximately fifty percent compared to a conventional planar cell utilizing identical wafer area.

Abstract: Quantum dot and quantum wire semiconductors in the nanosize range are produced by a process which utilizes a microporous aluminum oxide surface layer on an aluminum metal substrate as a template for the semiconducting material. The microporous surface layer is prepared by anodizing an aluminum substrate in an acid bath. Then a metal capable of forming a semiconductor compound is electrodeposited into the surface micropores, the oxide is partially or wholly etched away, and the deposited metal is reacted with a liquid or gaseous reagent to convert it chemically to a semiconducting compound. By the process of the invention, there are produced quantum dot or quantum wire semiconductors in the form of an array of substantially mutually parallel, substantially uniform-sized rods of semiconductor material protruding from an electrically conductive substrate, each rod having a diameter less than 100 nanometers.

Abstract: The invention relates to a method of scribing and separating dice from each other after fabrication in a semiconductor wafer in a manner such that active circuit regions in the dice reside as near to an edge of a die as possible. The wafer is anistropically etched through the active layer and into the substrate through an opening in the mask to form a generally V-shaped channel with the dice then being separated along a vertex of the channel. The dice are then positioned to abut each other in the form of a mosaic.

Abstract: Installation (10) for processing of successive wafers (26) under pulsating double-floating condition within processing gaps (174) and (176) above and underneath such wafer of an at least almost entirely sealed-off processing chamber (24) by means of a reciprocating upper chamber wall (34) immediately above this wafer, and with wafer supply and discharge toward and from this chamber also under pulsating double-floating condition.