Abstract: Prior to plasma etching, a wafer is placed on conductive support pins which extend through an electrostatic chuck. The electrostatic chuck is disposed on a susceptor incorporating a cooling jacket. A potential for electrostatic attraction is applied to the electrostatic chuck. The support pins are lowered while they are grounded, thus placing the wafer on the electrostatic chuck. Subsequently, the support pins are retracted into the electrostatic chuck to release contact between the wafer and themselves. A heat medium gas is then supplied between the wafer and the electrostatic chuck to improve the heat transfer rate therebetween. A plasma is then generated in a process chamber, and the wafer is etched by using the plasma. Since the heat transfer rate between the wafer and the electrostatic chuck is improved before the generation of the plasma, damage to the wafer due to heat can be prevented, and the starting time required to start an etching process is shortened.

Abstract: During the manufacture of a semiconductor device in a semiconductor substrate, masks of photoresist are used for selecting given regions to be processed. This photoresist is stripped by subjecting the semiconductor substrate in a processing chamber to an oxygen-containing plasma after-glow, that is passed over the photoresist. In order to limit the penetration of inorganic contaminations released from the photoresist into the silicon oxide layer of the semiconductor substrate, according to the invention, the semiconductor substrate is connected via a first electrode to the positive terminal and via a second electrode arranged at a certain distance therefrom in the processing chamber to the negative terminal of an electric supply source in such a manner that an electrical field is adjusted between the silicon oxide layer and the plasma. The second electrode may be the electrically conducting wall of the processing chamber.

Abstract: A ramp activated low temperature quality epitaxial growth process. A substrate is pre-conditioned and a passivation layer overlying the substrate surface is formed. The substrate is introduced into a process chamber having a controlled temperature. A process chamber purge technique is used to remove oxygen and contaminants from the process chamber before epitaxial growth begins. A process gas, which has an epitaxial growth species, a process chamber purging species and other possible species, is introduced into the process chamber at a low temperature. The process gas and the passivation layer keep the process chamber environment and the substrate surface free from contamination and free from native oxide growth before and, in some cases, during epitaxial growth. The process chamber temperature is gradually elevated to initiate a quality epitaxial growth by starting growth relative to decomposition of the passivation layer.

Abstract: A principal feature of the present invention is to clean a surface of a semiconductor substrate without providing a damaged layer to the surface thereof. A native oxide film formed on the surface of a silicon substrate is etched by plasma employing a gas containing fluorine. The surface of the semiconductor substrate is again subjected to plasma etching by employing a gas containing fluorine in order to remove a surface damaged layer and a fluorocarbon layer formed in the above step of plasma etching. The semiconductor substrate surface is irradiated with ultraviolet rays under a low pressure in order to dissociate and remove fluorine atoms chemically adsorbed to the semiconductor substrate surface upon the latter plasma etching.

Abstract: The present invention provides a dry etching method, having the steps of introducing a mixed gas consisting of a reactive gas and an inert gas into a plasma chamber for generating a plasma, with the partial pressure of each of these gas components being controlled, exciting the mixed gas within the plasma chamber so as to generate ionized particles and excited particles having high reactivity, withdrawing the particles generated in the plasma chamber into a sample chamber having a compound semiconductor substrate housed therein, and physically and chemically etching the compound semiconductor substrate with the particles.

Abstract: An improved method of fabricating integrated circuit structures on semiconductor wafers using a plasma-assisted process is disclosed wherein the plasma is generated by a VHF/UHF power source at a frequency ranging from about 50 to about 800 MHz. Low pressure plasma-assisted etching or deposition processes, i.e., processes may be carried out within a pressure range not exceeding about 500 milliTorr; with a ratio of anode to cathode area of from about 2:1 to about 20:1, and an electrode spacing of from about 5 cm. to about 30 cm. High pressure plasma-assisted etching or deposition processes, i.e., processes may be carried out with a pressure ranging from over 500 milliTorr up to 50 Torr or higher; with an anode to cathode electrode spacing of less than about 5 cm.

Abstract: A method of utilizing and etching SiO.sub.2 in the processing of semiconductor wafers comprises: a) providing a layer of undoped SiO.sub.2 atop a wafer; b) providing a layer of doped SiO.sub.2 atop the layer of undoped SiO.sub.2 ; and c) wet etching the layer of doped SiO.sub.2 selectively relative to the undoped layer of SiO.sub.2 utilizing an acid solution, the acid solution comprising a mixture of at least two different mineral acids provided in a selected ratio relative to one another, one of the mineral acids being HF. The preferred volumetric ratio of other mineral acids in the acid solution to HF in the acid solution is from 20:1 to 110:1, with a ratio of from 45:1 to 65:1 being most preferred. Example acids to be combined with the HF include H.sub.2 SO.sub.4, HCl, HNO.sub.3, H.sub.3 PO.sub.4, HBr, HI, HClO.sub.4, and HIO.sub.4, or mixtures thereof.

Abstract: A MOS-FET transistor is produced on a substrate made of glass which has a non single crystal semiconductor film (2'). The average diameter of a crystal grain in said film is in the range between 0.5 times and 4 times of thickness of said film, and said average diameter is 250 .ANG.-8000 .ANG. , and said film thickness is 500 .ANG.-2000 .ANG.. The density of oxygen in the semiconductor film (2') is less than 2.times.10.sup.19 /cm.sup.3. A photo sensor having PIN structure is also produced on the substrate, to provide an image sensor for a facsimile transmitter together with the transistors. Said film (2') is produced by placing amorphous silicon film on the glass substrate through CVD process using disilane gas, and effecting solid phase growth to said amorphous silicon film by heating the substrate together with said film in nitrogen gas atmosphere. The film (2') thus produced is subject to implantation of dopant for providing a transistor.

Abstract: Disclosed is a system, including both method and apparatus, for enhancing the plasma etching of a semiconductor wafer. The system enhances etchant uniformity while greatly reducing plasma contamination. Etching is performed in a housing for processing a semiconductor wafer having a wafer perimeter defined by an outer wafer edge, a top surface and a bottom surface. The plasma etch technique includes a plasma positioned substantially coplanar with and proximate to the semiconductor wafer. The plasma has a perimeter defined by an outer plasma edge and extending beyond substantially all of the wafer perimeter. Provided is a means for introducing an inert gas between the wafer perimeter and the plasma perimeter so the inert gas may or may not hit the wafer's bottom surface. Plasma and wafer can each have a circular shape where the plasma and the wafer are proximate to each other.

Abstract: The present invention provides a method for anisotropically dry etching a substrate, in which the substrate is brought into a processing area; a vacuum is applied over the processing area; and an audio frequency signal is applied at the electrodes of the processing area; such as to create a plasma at the processing area, having a power density substantially above 0.01 Watts/cm.sup.3. Further, an apparatus for carrying out this method comprises a self-DC-bias on the cathode.

Abstract: A process for etching a silicon dioxide layer is disclosed. The novel two step etch process is used, for example, to perform a contact etch through a BPSG layer. Both etch steps are carried out in a flow of O.sub.2 and CHF.sub.3. In the first step, a high flow rate of oxygen (approximately 19 SCCM) is used. During this step, the bulk of the oxide is removed, without the problem of micro masking wherein small localized regions remain partially un-etched. In the second step, the remaining oxide is removed in a lower O.sub.2 flow rate, giving good oxide to silicon selectivity.

Abstract: There is disclosed a container which conveys a semiconductor wafer and in which the face of the wafer is chemically treated. The container comprises a receiving platelike member and a cover made from a transparent or semitransparent plastic. The platelike member is made from a hydrophobic plastic such as a fluorocarbon resin and provides a quite small area in contact with the sample of the wafer to support it. Tonguelike portions extend steeply upwardly around the sample. When the cover is closed, the tonguelike portions are thrown toward the center of the container, bent, and pressed against the side surface of the sample. The container locks the sample without making contact with the face of the sample. The top cover is fitted over the platelike member to maintain the airtightness. To assure the airtightness, the container is equipped with an O ring and a tightening implement.

Abstract: Method of forming a thin film consisting of a silicon-based material includes a first step of setting a substrate subjected to formation of a thin insulating film consisting of the silicon-based material in a chamber having high-frequency electrodes for receiving a high-frequency power while the substrate is kept heated at a predetermined temperature, a second step of supplying a process gas to the chamber, a third step of applying a high-frequency power to the high-frequency electrodes to generate a plasma, a fourth step of depositing an insulator consisting of the silicon-based material on the substrate to a predetermined thickness while gas supply in the second step and supply of the high-frequency power in the third step are kept maintained, and a fifth step of cooling the substrate on which the insulating film is formed and unloading the substrate from the chamber. In the fourth step, the substrate is kept heated within the temperature range of 230.degree. C. to 270.degree. C.

Abstract: A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed areas (46) as stripes or a matrix, and protected areas. Sidewall spacers (44) of predetermined thickness (52) with inner surfaces (48) contact the protective layer sidewalls. A first trench (50) is formed in substrate areas (46) with sidewalls aligned to the sidewall spacer outer surfaces (47) and extending depthwise through the P-body layer (26) to at least a predetermined depth (56). Gate oxide (60) is formed on the trench walls and gate polysilicon (62) refills the trench to a level (64) near substrate upper surface (28). Oxide (68) between sidewall spacers (44) covers polysilicon (62). Removing the protective layer exposes upper substrate surface (28') between spacer inner surfaces (48).

Abstract: For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.2 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.

Abstract: In the manufacture of integrated circuits, a process for forming a dielectric layer such as silicon dioxide which has a high wet etch rate is disclosed. Illustratively, the process is performed with a precursor gas in a plasma reactor with a shower head and a susceptor which supports a wafer. The power density, pressure, susceptor-shower head spacing, and (optionally) temperature are respectively decreased, decreased, increased and decreased to reduce the effectiveness of dissociation of the precursor gas. The resulting film contains impurities which enhance its wet etch rate.

Abstract: The state of conduction of an MOS transistor 11 is definitively controlled by a laser beam 21, by forming an electrical connection 22 between the gate 16 and the subjacent portion d of the source region 14 or drain region 15. The invention is applicable in particular to the correction (reconfiguration, redundancy) of integrated circuits and to the programming of integrated PROMs.

Abstract: A process chamber purge module (56) is provided, including a stack module (60) and a process chamber liner (62). The stack module comprises a plurality of quartz plates (100, 110, and 116) having flow apertures to permit radial and axial flow of a purge gas to the backside of a semiconductor wafer (18). The process chamber liner (62) isolates the process chamber walls from the process chamber process environment by flowing between the liner and the walls a portion of the purge gas. Process chamber liner (62) comprises a quartz cylindrical collar that operates to decouple the process chamber (16) process environment (20) from the process chamber collar walls (42). The stack module (60) decouples the process chamber optical/vacuum quartz window (64) from the semiconductor wafer (18) during a heated semiconductor wafer fabrication process. By flowing purge gas to the backside of the semiconductor wafer (18), the present invention prevents reactive process gas interaction with the semiconductor wafer backside.

Abstract: The present invention features new etchants to be utilized in the etching, depositing and growth processes for fabricating integrated circuits. The etchants contain a new family of compounds consisting of a single molecule. The molecule contains several halogen atoms, thus eliminating the need to add chlorine compounds in admixture with fluorine etchant materials. The new materials provide selectivity in the etching and deposition processes, as well as high product yield with high throughput. The etchants of this invention consist of a single amine molecule containing both fluorine and another halogen atom, consisting of chlorine or bromine, which are attached covalently to a nitrogen base atom. The basic formula for the molecule of this invention is given by: ##STR1## where: Z=chlorine or brominey=1 or 2;x=1 or 2; andx+y=3.

Abstract: Disclosed herein are an insulating film forming method for semiconductor device interconnection and a plasma treatment system for use in the method. The method comprises (i) a step of forming an insulating film free of void, on a substrate having an interconnection pattern, in which a mixed gas of a film forming source gas and an etching gas comprising a fluorine compound is used to perform both deposition of an insulating film by plasma CVD and reactive etching of the insulating film, simultaneously, and (ii) a step of planarizing the surface of the insulating film formed by the step (i) and comprised of, for example, silicon oxide, in which a gas of a material decomposable by a reactive gas capable of decomposing the insulating film is supplied onto the substrate so as to deposit a solid film of the material, e.g. Si(OCH.sub.3).sub.