Abstract: A silicone resin is applied on a substrate to form a coating film. The coating film is subjected to a reactive ion etching in an atmosphere containing at least O.sub.2. Thus, the film is inorganized in its surface and has a distribution of the residue, an organic radical, contained therein gradually increasing in the depth thereof. This permits an insulating film having excellent heat endurance to be formed without generation of any cracks. This insulating film is very useful as an interlayer insulating film for multi-layer wiring.

Abstract: A method of producing insulating layers over a semiconductor substrate comprising spinning a film of spin-on-glass (SOG) over a semiconductor substrate, precuring the film of SOG at an elevated temperature sufficient to remove the bulk of solvent and curing the film of SOG in a plasma in a plasma reactor of a type exhibiting a self-biased R.sub.F discharge adjacent the SOG for a period of time sufficient to exclude the bulk of SiOH, organic volatiles and H.sub.2 O from the layer.

Abstract: The invention is to a method for plasma spraying a ceramic or plastic material on selected areas of leads to form stabilizer/spacers for the leads.

Abstract: A method of processing a semiconductor wafer using a wafer chuck having a first end with a non-planar surface, the non-planar surface shaped such that a wafer supported at a plurality of points about its periphery will have a uniform pressure between its surface and the non-planar surface, and pressing a surface of the wafer against the non-planar surface of the wafer chuck.

Abstract: For dry-etching a material such as an aluminum alloy layer, a helium gas is added to an etching gas to detect an end point of etching in the material. When the dry-etching of the material has been completed, an emission spectrum intensity of helium having a single peak occurs.

Abstract: Nanocrystals of semiconductor compounds are produced. When they are applied as a contiguous layer onto a substrate and heated they fuse into a continuous layer at temperatures as much as 250, 500, 750 or even 1000.degree. K below their bulk melting point. This allows continuous semiconductor films in the 0.25 to 25 nm thickness range to be formed with minimal thermal exposure.

Abstract: For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to .about.10.sup.16 /cm.sup.2 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.

Abstract: A method of treating a substrate with substantially equal flow rates of treatment gases in a treatment chamber containing the substrate. Because the times during which the treatment gases pass through pipes are controlled, even when the flow rates of the treatment gases differ appreciably, the impurity concentration in a film near the interface between the substrate and the film reaches a desired concentration. Also, when the times during which the treatment gases pass through the pipes are short, the treatment gases are unlikely to adhere to the walls of the pipes. It is thus possible to reduce the frequency of dummy runs.

Abstract: A wafer processing cluster tool, having one or more load-locks, is provided with one or more batch preheating modules that receive wafers only from the cluster tool transport module at the internal vacuum pressure of the machine. The loading, unloading, handling and processing of wafers in the machine can occur while other wafers are being preheated. The preheat module has a vertically moveable rack and is loaded with various sized batches of wafers with no vacant positions between them. Wafer shaped shields may occupy positions adjacent top and bottom wafers to cause them to heat the same as other wafers in the rack. Infrared lamps positioned outside of quartz windows heat wafers in the preheat module. The rack may rotate to improve heating uniformity. Temperature sensors, such as pyrometers, that do not contact the wafers being preheated, measure temperature for control of the heating of the lamps.

Abstract: A manufacturing system for processing semiconductor wafers through a plurality of processing stations that perform manufacturing operations on wafers includes a plurality of processing stations, each of which are capable of performing at least one processing operation of a wafer, each of the processing stations having a controlled environment for processing the wafers, and a branched track providing a surface leading to each of said processing stations. On the track there are provided a plurality of guided transport vehicles adapted to travel between the process stations. A plurality of wafer carriers, each adapted to support a single wafer and be carried by the transport vehicles, are part of the system. An interface is provided at each processing station to introduce the wafer from the box into the clean environment of the process station, and subsequently return the box and wafer to the transport vehicle.

Abstract: The present invention relates to a method of manufacturing a semiconductor integrated device and, more particularly, to a semiconductor integrated device having NPN and PNP power and logic devices combined with complementary MOS and DMOS devices. The present invention is a multipitaxial process for fabricating a high power/logic complementary bipolar/MOS/DMOS (CBiCMOS) integrated circuit. The process steps for fabricating the novel integrated circuit combines on the same substrate complementary high power, logic/analog bipolar transistors with complementary MOSGVm devices and DMOSFET devices. The present invention optimizes the characteristics of these different transistors in a single process flow. The present high power/logic CBiCMOS multiepitaxial process results in device structures having distinct technical advantages over prior art processes and structures heretofore known.

Abstract: A method for forming a dielectric layer in an integrated circuit is disclosed. After a first dielectric layer is formed, a second dielectric layer is formed on top of the first layer. The second layer is formed by reducing precursor gas flow during the initial portion of the deposition process so that the initial film density of the deposited dielectric is higher or equal to the density of the bulk of the first and second dielectric.

Abstract: A LPCVD-process for SiO.sub.2 -layers at a deposition temperature between 420.degree. C. and 500.degree. C., using a silane compound in which only one H and one Cl-atom is bonded to the Si-atom yields a very satisfactory uniformity of the layer thickness. An example of such a silane compound is dimethyl monochlorosilane.

Abstract: A method and apparatus for enhanced doping of IIB-VIA semiconductors through the use of a free-radical source is described. The process involves the simultaneous production of beams of free-radicals together with group IIB molecules or atoms and group VIA molecules or atoms in a standard molecular beam epitaxy crystal growth system. These beams react on a substrate producing single crystal films of doped IIB-VIA semiconductors such as ZnSe:N, for example. The improved doping characteristics result from the high reactivity of radicals produced by the free-radical source with the surface of the growing crystal.

Abstract: A processing apparatus and method wherein a wafer is exposed to activated species generated by a first plasma which is separate from the wafer, but is in the process gas flow stream upstream of the wafer, and is also exposed to plasma bombardment generated by a second plasma which has a dark space which substantially adjoins the surface of the wafer. The in situ plasma is relatively low-power, so that the remote plasma can generate activated species, and therefore the in situ plasma power level can be adjusted to optimize the plasma bombardment. Ultraviolet light to illuminate the face of a wafer being processed is generated by a plasma which is within the vacuum chamber but is remote from the face of the wafer. It is useful to design the gas flow system such that the ultraviolet-generating plasma has its own gas feed, and the reaction products from the ultraviolet-generating plasma do not substantially flow or diffuse to the wafer face.

Abstract: A thin film silicon semiconductor device provided on a substrate according to the present invention comprises a thin polycrystalline silicon film having a lattice constant smaller than that of a silicon single crystal and a small crystal grain size. This thin polycrystalline silicon film can be obtained by depositing a thin amorphous silicon film in an inert gas having a pressure of 3.5 Pa or lower by a sputtering deposition method and annealing the thin amorphous silicon film for a short time of 10 seconds or less to effect polycrystallization thereof. A thin film silicon semiconductor device comprising such a thin polycrystalline silicon film having a small lattice constant has excellent characteristics including a carrier mobility of 100 cm.sup.2 /V.multidot.s or higher.

Abstract: A method for forming a thin high quality interlevel dielectric is disclosed. The dielectric is produced in a plasma reactor utilizing a precursor gas such as TEOS. Pressure, power, temperature, gas flow, and showerhead spacing are controlled so that a dielectric of TEOS may be deposited at 60-5 .ANG. / sec, thus making formation of thin (800 .ANG.) high quality dielectrics feasible.

Abstract: A method for providing superior fill of features in semiconductor processing utilizes a laser ablation system. Deposition is obtained by ablating target materials which are driven off perpendicular to the target in the direction of the deposition surface. The method provides complete fill of high aspect ratio features with nominal heating of the substrate. Alloys and graded layers, as well as pure metals, can be deposited in low temperature patterned layers. In addition, the system has been used to achieve superior trench filling for isolation structures.

Abstract: A semiconductor device manufacturing process and a bias ECRCVD apparatus for the process. The semiconductor device manufacturing process comprises the steps of forming trenches in the surface of a substrate, forming an insulating film by bias ECRCVD over the surface of the substrate, etching the insulating film by lateral leveling etching so as to expand the width of grooves formed in portions of the insulating film which are formed in regions other than those corresponding to the trenches, masking the portions of the insulating film which fill the trenches and removing the portions of the insulating film formed in the regions other than those corresponding to the trenches.

Abstract: A plasma enhanced chemical vapor deposition (PECVD) process for producing an amorphous semiconductive surface coating consisting essentially of hydrogenated silicon carbide (a-SiC:H) having an improved blood compatibility, the process including positioning a substrate to be coated in a reactor chamber; heating the substrate to a substrate temperature ranging from 0.degree. C. to 350.degree. C.; providing a flow of a reactive gas mixture including from about 50 to about 100% of methane (CH.sub.4), from about 0 to about 50%, of silane (SiH.sub.4), and from about 0 to about 2% of phosphine (PH.sub.3), the flow having a flow rate based on a flow rate of silane (SiH.sub.4) which ranges from 10 to 50 sccm, the methane (CH.sub.4) and the phosphine (PH.sub.3) having respective flow rates which are based on the flow rate of the silane (SiH.sub.4); introducing the flow of the reactive gas mixture into the reactor chamber to provide a process pressure ranging from 0.