Abstract: A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout. The method further includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout. The method also includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout.

Abstract: A system and method for characterizing a memory instance. Characterizing a memory instance includes obtaining a memory instance comprising a plurality of leaf cells. Each of the plurality of leaf cells comprises components. First channel connected components from the components within each of the plurality of leaf cells are determined, and a first super leaf cell is generated by combining a first two or more leaf cells of the plurality of leaf cells based on the first channel connected components. Further, an updated memory instance is generated based on the first super leaf cell, and a timing model is determined for the updated memory instance.

Abstract: Various aspects of the present disclosed technology relate to techniques for classifying layout patterns. First, a set of density feature vectors for a set of layout regions in the layout design are extracted using a set of rings. Each component of a density feature vector in the set of density feature vectors corresponds to a ring in the set of rings. The set of rings do not overlap with each other and cover a whole area of a circle when being placed together. Next, a machine learning-based clustering process is performed to separate layout features in the set of layout regions into clusters of layout features based on the set of density feature vectors. Each of the clusters of layout features may be further divided into subclusters based on one or more properties.

Abstract: A method of determining a relationship between a stochastic variation of a characteristic of an aerial image or a resist image and one or more design variables, the method including: measuring values of the characteristic from a plurality of aerial images and/or resist images for each of a plurality of sets of values of the design variables; determining a value of the stochastic variation, for each of the plurality of sets of values of the design variables, from a distribution of the values of the characteristic for that set of values of the design variables; and determining the relationship by fitting one or more parameters from the values of the stochastic variation and the plurality of sets of values of the design variables.

Abstract: A simulation management service receives a request to perform reinforcement learning for a robotic device. The request can include computer-executable code defining a reinforcement function for training a reinforcement learning model for the robotic device. In response to the request, the simulation management service generates a simulation environment and injects the computer-executable code into a simulation application for the robotic device. Using the simulation application and the computer-executable code, the simulation management service performs the reinforcement learning within the simulation environment.

Abstract: Methods of semiconductor device fabrication are provided. In an embodiment, a method of semiconductor device fabrication includes receiving a first mask design comprising a first mask function, determining a transmission cross coefficient (TCC) of an exposure tool, decomposing the TCC into a plurality orders of eigenvalues and a plurality orders of eigenfunctions, calculating a kernel based on the plurality orders of eigenvalues and the plurality orders of eigenfunctions; and determining a first sub-resolution assist feature (SRAF) seed map by convoluting the first mask function and the kernel.

Abstract: Training data may be collected based on a set of test-case configurations for each integrated circuit (IC) design in a set of IC designs. The training data may include a set of features extracted from each IC design, and a count of test cycles required for achieving a target test coverage for each test-case configuration. A machine learning (ML) model may be trained using the training data to obtain a trained ML model. The trained ML model may be used to predict a set of ranked test-case configurations for a given IC design based on features extracted from the given IC design.

Abstract: The present disclosure describes an integrated circuit device that includes a digital signal processing (DSP) block. The DSP block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Also, the first plurality of inputs, the second plurality of inputs, or both are derived from higher precision values. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

Abstract: A processor may identify that a computing device is below a power threshold. The processor may generate a charge request. The charge request may include metrics associated with a requested power exchange. The processor may send the charge request to a decentralized exchange. The decentralized exchange may include the computing device and at least two other devices. The processor may receive respective charging proposals from the at least two other devices. The processor may select one of the respective charging proposals.

Abstract: Predictive multi-planar semiconductor manufacturing systems and methods are provided including a processor, an artificial intelligence unit in communication with the processor, and a computer readable memory with processing instructions in communication with the processor. The manufacturing system receives and analyzes semiconductor design and manufacturing process rules and data and dimensions for a user's desired semiconductor. The artificial intelligence unit is configured to run simulations trying multiple three-dimensional, multi-planar shapes and analyzing for highest surface area yield based on the design and manufacturing process rules and data and the dimensions. The artificial intelligence unit is further configured to determine a three-dimensional, multi-planar shape for the desired semiconductor to optimize surface area based on the simulations and to construct the three-dimensional, multi-planar shape that optimizes surface area.

Abstract: The present disclosure relates to applying genetic optimization to a routing strategy associated with an electronic design. Embodiments may include receiving pin and net information from an electronic design file and determining a minimum spanning tree for all pins associated with each net. Embodiments may include identifying pairs of connected pins and representing the pins as at least one line segment without layer information. Embodiments may include generating a crossing map based upon the line segments and assigning random layer information to each of the line segments. Embodiments may further include performing crossover and mutation operations to the line segments using hyperparameters and evaluating a fitness of the line segments. Embodiments may also include instantiating vias based upon a layer to which the line segment was assigned.

Abstract: A design management apparatus (100) includes a conversion unit (12) and a test unit (13). The conversion unit (12) generates model information (403) that is a format of design information (303) being converted, the design information (303) being the design information (303) created in a process of mechanical design in an engineering chain, and generates model information (405) that is a format of design information (305) being converted, the design information (305) being the design information (305) created in a process of control design in the engineering chain. The test unit (13) associates the model information (403) and the model information (405) using entire reference information (22) that associates the model information (403) and the model information (405), and tests for consistency between the model information (403) and the model information (405) associated.

Abstract: Security measures for signal paths with tree structures can be implemented at design phase using an EDA software program or tool with security feature functionality that, when executed by a computing system, directs the computing system to: display a canvas through which components of a circuit are arranged; and provide a menu of commands, including an option to add components from a library to the canvas and an option to secure a tree. In response to receiving a selection of the option to secure the tree, the system can be directed to add a hardware countermeasure coupled to at least two lines or terminal nodes of a tree structure identified from components on the canvas or in a netlist corresponding to a circuit's design.

Abstract: A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.

Abstract: A battery case has first and second coils on opposing sides of a battery and has switching circuitry that is coupled between the first and second coils. The battery case has a battery that provides supplemental battery power wirelessly to a wireless power receiving device via the second coil when the switching circuitry is in an open state. The case can also receive power wirelessly with the first coil from a wireless charging mat when the switching circuitry is in the open state. In a closed state, the switching circuitry shorts the first and second coils together so that current flowing through the first coil flows through the second coil in series and so that wireless power from the wireless charging mat that is received with the first coil is transmitted wirelessly to the wireless power receiving device using the second coil.

Abstract: A method is disclosed for creating a flattened version of a three-dimensional electrical harness assembly design in a computer-aided design environment. The method includes storing data in computer memory including route segment identifiers, diameters, lengths, and end points for route segments in the electrical harness assembly. A computer processor designates route segments as forming a trunk line of the electrical harness assembly, based on the stored data, and produces a flattened two-dimensional version of the design. All the route segments designated as forming the trunk line are represented in the flattened 2D version by straight connected lines, having a particular orientation (e.g., horizontal), and every other route segment is represented as extending out from the trunk line. The flattened 2D version is displayed on a display screen of a computer.

Abstract: Techniques and systems for generating constrained random stimuli during functional verification of a design under verification (DUV) are described. Some embodiments can compute an observed probability distribution for each variable in a set of variables based on at least a first random solution generated using a set of constraints that are defined over the set of variables. The embodiments can then compute a correction probability distribution for each variable in the set of variables based on the observed probability distribution and an intended probability distribution. Next, while generating at least a second random solution using the set of constraints, the embodiments can select a random value for a given variable in the set of variables based on the correction probability distribution for the given variable. The observed probability distribution can be continuously updated and stored as constrained random stimuli are generated.

Abstract: A method includes forming a first mandrel pattern and a second mandrel pattern. The first mandrel pattern includes at least first and second mandrels for a mandrel-spacer double patterning process. The second mandrel pattern includes at least a third mandrel inserted between the first and second mandrels. The first mandrel pattern and the second mandrel pattern include a same material. The first and second mandrels are merged together with the third mandrel to form a single pattern.

Abstract: Systems and methods for adjusting a digital circuit design are described. For example, the method may include selecting a first path in the digital circuit design. The first path includes a plurality of gates. The method also includes generating a k-hop neighborhood graph of the first path, encoding the k-hop neighborhood graph into a state vector, and applying a machine learning model to the state vector to determine an adjustment to be made on a first gate of the plurality of gates. The method further includes changing the first gate based on the adjustment.

Abstract: The present disclosure relates to routing superconducting wires in superconducting circuits and in particular to efficiently routing superconducting wires that meet inductance requirements. The superconducting wire routing technique involves modeling the target location not only as a physical location, but as a physical location (e.g., x, y, and z dimensions) combined with inductance (e.g., a target inductance range). One or more other constraints may also be included in the modeling, such as a number of wires that would need to be moved/lifted, a number of circuit-vias allowing passage through layers of the circuit, an amount of cross-coupling with other inductors, and a number of wire segments.