Abstract: An excitation source planning method for an electrical stimulation is proposed to plan an excitation source. A layout importing step is performed to drive a processing unit to import a PCB layout to an electromagnetic simulation software module. A port establishing step is performed to set the excitation source to be vertically disposed between a signal layer and a main ground layer. A model generating step is performed to perform the electrical simulation according to the excitation source to generate a three-dimensional simulation model corresponding to the PCB layout. When the signal layer is not electrically connected to the main ground layer, the electromagnetic simulation software module executes an extending step. The extending step is performed to provide a first metal unit to be connected to the signal layer, and reset the excitation source to be vertically disposed between the first metal unit and the main ground layer.

Abstract: A method and apparatus for automatically generating periodic boiler combustion models and aperiodic boiler combustion models through automatic learning are provided. The method of automatically generating a boiler combustion model may include determining whether a specific event has occurred in association with a boiler, changing a training condition according to a result of the determining, generating a boiler combustion model trained on operation data measured in the boiler and stored in a database according to the training condition, and determining a precision of the generated boiler combustion model.

Abstract: Methods, machine readable media and systems for performing side channel analysis are described. In one embodiment, a method can determine, from a gate level representation of a circuit in a layout on a die of an IC, a first set of paths through the circuit that process security related data during operation of the circuit, the circuit including a second set of paths that do not process security related data; and the method can further determine, in a simulation of power consumption in the first set of paths but not the second set of paths, power consumption values in the first set of paths to determine potential security leakage of the security related data in the circuit. The method can further determine, from the power consumption values, positions in the layout for inserting virtual probes on the die for use in measuring security metrics that indicate potential leakage of the security related data. The insertion of the virtual probes is relative to the actual simulated layout of the die.

Abstract: Methods, systems and apparatus for performing windowed quantum arithmetic. In one aspect, a method for performing a product addition operation includes: determining multiple entries of a lookup table, comprising, for each index in a first set of indices, multiplying the index value by a scalar for the product addition operation; for each index in a second set of indices, determining multiple address values, comprising extracting source register values corresponding to indices between i) the index in the second set of indices, and ii) the index in the second set of indices plus the predetermined window size; and adjusting values of a target quantum register based on the determined multiple entries of the lookup table and the determined multiple address values.

Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.

Abstract: A true random metastable flip-flop (TRMFF) compiler generates an electrical architecture for a TRMFF chain. The compiler selects components for the TRMFF chain from a library of standard cells and logically connects these components in accordance with a primitive polynomial to generate the electrical architecture. The TRMFF chain provides a sequence of random numbers from one or more physical processes in accordance with the primitive polynomial. During operation, one or more microscopic phenomena inside and/or outside of the TRMFF chain can cause one or more low-level, statistically random entropy noise signals to be present within the TRMFF chain. The TRMFF chain advantageously utilizes the one or more low-level, statistically random entropy noise signals to provide the sequence of random numbers.

Abstract: An electronic device includes a display, a conductive coil, a wireless charging circuit electrically connected to the conductive coil, a power management circuit, a battery; and a processor, wherein the processor may be configured to control the electronic device to: measure a current flowing from the power management circuit to the wireless charging circuit while power is transferred to an external device through the conductive coil, and adjust the power transferred to the external device through the conductive coil based on a part of a power amount preset in a signal requesting addition of power based on a value of the current being between a first threshold value and a second threshold value greater than the first threshold value.

Abstract: There are provided a learning apparatus, a learning method, and a program that enable, by using one type of device data, learning of a plurality of models using different data formats. A learning data acquiring section (36) acquires first data that is first-type device data. A first learning section (42) performs learning of a first model (34(1)) in which an estimation using the first-type device data is executed by using the first data. A learning data generating section (40) generates second data that is second-type device data the format of which differs from the format of the first-type device data on the basis of the first data. A second learning section (44) performs learning of a second model (34(2)) in which an estimation using the second-type device data is executed by using the second data.

Abstract: The present disclosure provides a circuit for balancing voltages of battery packs to be connected in parallel, comprising: IN-side switches and OUT-side switches; a DC-DC converter with an IN terminal connected to the IN-side switches and an OUT terminal connected to the OUT-side switches; and a controller to operate an IN-side switch to connect a Vmax battery pack to the IN terminal, operate an OUT-side switch to connect a Vmin battery pack to the OUT terminal, and activate the DC-DC converter to transfer energy from the Vmin battery pack to the Vmin battery pack. The controller responds to an IN terminal voltage being sufficiently close to a voltage of a first battery pack by operating an IN-side switch to connect the first pack to the IN terminal, and responds to an OUT terminal voltage being sufficiently close to a voltage of a second battery pack by operating an OUT-side switch to connect the second battery pack to the OUT terminal.

Abstract: A security verification system performs security verification of a circuit design. The security verification system simplifies formal security verification of the circuit design by replacing circuit blocks of the circuit with black box circuit blocks. The security verification system instruments the circuit design so that black-boxing can be performed for security verification without changing the security decision over the data paths. The security verification system uses dependence information of the inputs and outputs of the black box to connect inputs of the circuit block with outputs of the circuit block. The black-box circuit block keeps the logic inside the cone of influence of clocks and resets. The system performs security verification of the circuit design by proving a non-interference property of the instrumented circuit design.

Abstract: Methods, systems and apparatus for simulating quantum circuits including multiple quantum logic gates. In one aspect, a method includes the actions of representing the multiple quantum logic gates as functions of one or more classical Boolean variables that define a undirected graphical model with each classical Boolean variable representing a vertex in the model and each function of respective classical Boolean variables representing a clique between vertices corresponding to the respective classical Boolean variables; representing the probability of obtaining a particular output bit string from the quantum circuit as a first sum of products of the functions; and calculating the probability of obtaining the particular output bit string from the quantum circuit by directly evaluating the sum of products of the functions. The calculated partition function is used to (i) calibrate, (ii) validate, or (iii) benchmark quantum computing hardware implementing a quantum circuit.

Abstract: Systems, computer-implemented methods, and computer program products that can facilitate determining a state of a qubit are described. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a relation determining component that can determine relation of a status signal of a quantum computing device to a noise value of the quantum computing device. The system can further include an operation time estimator that can estimate an operation time for the quantum computing device based on the relation of the status signal to the noise value.

Abstract: A method for generating a model of a transistor includes: initializing hyper-parameters; training the neural network in accordance with the hyper-parameters and training data relating transistor input state values to transistor output state values to compute neural network parameters; determining whether the transistor output state values of the training data match an output of the neural network; porting the neural network to a circuit simulation code to generate a ported neural network; simulating a test circuit using the ported neural network to simulate behavior of a transistor of the test circuit to generate simulation output; determining whether a turnaround time of the generation of the simulation output is satisfactory; in response to determining that the turnaround time is unsatisfactory, re-training the neural network based on updated hyper-parameters; and in response to determining that the turnaround time is satisfactory, outputting the ported neural network as the model of the transistor.

Abstract: The present disclosure provides a wireless charging device and method, and a device to be charged. The wireless charging device includes a first communication control circuit. The device to be charged includes a second communication control circuit and a battery. The first communication control circuit performs wireless communication with the second communication control circuit during wireless charging of the battery. The wireless communication may be one or more of Bluetooth communication, Wi-Fi communication, short-range wireless communication based on a high carrier frequency, optical communication, ultrasonic communication, ultra-wideband communication and mobile communication.

Abstract: A system and method are provided to enable non-quantum experts to schematically represent, simulate and quantify the performance of physically realistic photonic quantum circuits. The framework offers the flexibility for users—not necessarily familiar with the fundamentals of quantum mechanics—to create circuits and work with simple inputs and outputs, while the complexities of manipulating high dimensionality quantum Hilbert spaces supporting photonic and physical quantum object states are handled with the use of purpose-built tools. The tools include a user-friendly method for defining classical photonic circuits which may be coupled to physical objects such as qubits, quantum input states, as well as classical and quantum measurement devices. The tools feature classical-to-quantum S-matrix conversion, quantum S-matrix extraction, as well as capabilities for defining and extracting quantum error parameters.

Abstract: A data processing apparatus in which a trade-off between over-learning prevention and calculation load prevention is eliminated when creating a model formula is provided.

Abstract: A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.

Abstract: A variational quantum algorithm is solved using two types of quantum processing units (QPU) with different performance metrics (e.g., speed, size and fidelity). One type of quantum processing unit (QPU) is used to optimize some or all of the circuit parameters in a first stage, and these are then used with a different type QPU in a second stage to solve the target problem. The different performance metrics permit tradeoffs between the two stages.

Abstract: Methods, machine readable media and systems for performing side channel analysis are described. In one embodiment, a method, performed on a data processing system, can receive input data that contains an RTL representation of a design of a circuit and then determine, from the input data, a set of registers that store security related data during operation of the circuit, wherein the set of registers are a subset of all of the registers in the design. The method then determines, in a simulation of power consumption of the set of registers in the RTL representation, security metrics that indicate a level of potential leakage of security related data such as secret or private cryptographic keys.

Abstract: A charging device for wirelessly charging an electronic device has a wireless power receiver antenna. The charging device includes a battery having a front surface and a back surface. The charging device has a first antenna comprising a wireless power transmit antenna or a dual-mode antenna. The first antenna is configured to wirelessly transmit power. The charging device has a second antenna. The second antenna includes a wireless power receiver antenna or a dual-mode antenna. The first antenna is configured to wirelessly receive power. The charging device also includes a housing encapsulating the battery, the first antenna, and the second antenna. The housing has a front contact surface opposed to a rear surface, and the contact surface has a coupling portion configured to couple the charging device with the electronic device. The first antenna is closer to the contact surface, and the second antenna is closer to the rear surface.