Abstract: An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises a routing topology for a net comprising interconnections between a set of pins. The IC design further comprises a set of candidate locations for inserting buffers. A set of cells from a cell library in memory is accessed. A candidate location from the set of candidate locations is assessed to determine whether at least one cell in the set of cells fits at the location. Based on determining that at least one cell in the set of cells fits at the candidate location, the location is marked as bufferable. A largest cell width that fits at the candidate location is determined based on the set of cells and a buffering solution is generated for the net using the largest cell width as a constraint on buffer insertion performed at the candidate location.

Abstract: A system and method for providing formal property verification across circuit design versions is described. In one embodiment, the system receives a first version and a second version of a circuit design. The received first version has a first set of constraints, a first set of next-state functions representing the first version of the circuit design, and a first property that has been verified as true for the first version of the circuit design. The received second version has a second set of constraints, a second set of next-state functions representing the second version of the circuit design, and a second property for the second version of the circuit design. The described embodiments further construct a composite circuit design based on the first set of constraints, the first set of next-state functions, and the first property and further based on the second set of constraints, the second set of next-state functions, and the second property.

Abstract: A design for an analog mixed-signal (AMS) circuit is accessed. An assertion for verifying the behavior of an analog signal in the AMS circuit is also accessed. The assertion is expressed in an assertion language for AMS circuits. A processor verifies the assertion against the predicted behavior of the analog signal in the AMS circuit. In various embodiments, the assertion language contains predefined classes for assertions in the temporal domain, for assertions in the frequency domain, and for assertions based on functional dependencies of an output analog signal on an input analog signal.

Abstract: A method and system for generating a clock distribution circuit for each macro circuit in an ASIC design are disclosed herein. In some embodiments, a method for generating a clock distribution circuit receives the ASIC design specified in a hardware description language (HDL), places each macro circuit in allocated locations on a semiconductor substrate, generates a custom clock skew information for each macro circuit based on a macro clock delay model, generates a clock distribution circuit for each macro circuit placed on the semiconductor substrate based on the generated custom clock skew information, modifies the clock distribution circuit if the generated clock distribution circuit does not meet timing requirements of the ASIC design, and outputs a physical layout of the ASIC design for manufacturing under a semiconductor fabrication process.

Abstract: A numerical information generating apparatus receives information of a programmable logic integrated circuit that includes a plurality of crossbar switches each including resistance change elements, calculates, for each of the plurality of crossbar switches, a base delay that is a delay in which influence of a load capacitance of other crossbar switch is excluded and a correction delay that is a delay caused by influence of a fanout of other crossbar switch, and further calculates a delay of each of the plurality of crossbar switches based on the base delay and the correction delay corresponding to each of the plurality of crossbar switches.

Abstract: Methods and systems for verifying that logic for implementing a pipelined process in hardware correctly moves data through the pipelined process. The method includes: (a) monitoring data input to the pipelined process to determine when watched data has been input to the pipelined process; (b) in response to determining the watched data has been input to the pipelined process counting a number of progressing clock cycles for the watched data; and (c) evaluating an assertion written in an assertion based language, the assertion establishing that when the watched data is output from the pipelined process the counted number of progressing clock cycles for the watched data should be equal to one of one or more predetermined values.

Abstract: A method for generating an augmented reliability performance model for a product includes obtaining a reliability performance model for the product, developing a reliability prediction machine learning model for predicting reliability performance of the product based on data obtained from manufacturing and testing of the product, and obtaining, from development of the machine learning model, feature names for the machine learning model and their predictive power values. The feature names may correspond to features from the data obtained from manufacturing and testing of the product. The method may further include extracting a set of feature names corresponding to features having highest predictive power values from the feature names, and generating the augmented reliability performance model for the product by modifying the reliability performance model to incorporate model parameters derived from the set of feature names.

Abstract: A method of estimating a toggle count of a circuit, includes, in part, simulating the circuit to generate training data and an associated training toggle count of the internal nodes of the circuit in response to a test bench, training a neural network system to generate an estimate of the training toggle count in accordance with the training data and the associated training toggle count, simulating the circuit to generate simulation data in response to a first set of input values applied to the circuit, and invoking the trained neural network system to estimate a number of toggles of the internal nodes of the circuit from the simulation data. The training data may include, in part, values of input signals applied to the circuit and values of registers disposed in the circuit for a multitude of time stamps. The neural network system may include, in part, at least three layers.

Abstract: A Toffoli magic state to be injected in preparation of a Toffoli gate may be prepared using a bottom-up approach. In the bottom-up approach, computational basis states are prepared in a fault tolerant manner using a STOP algorithm. The computational basis states are further used to prepare the Toffoli magic state. The STOP algorithm tracks syndrome outcomes and can be used to determine when to stop repeating syndrome measurements such that faults are guaranteed to be below a threshold level. Also, the STOP algorithm may be used in growing repetition code from a first code distance to a second code distance, such as for use in the computational basis states.

Abstract: Methods for randomly storing data received at a plurality of silicon-based devices included in a matrix-computer-cluster are provided. The silicon-based devices may be arranged in predetermined rows within the matrix-computer-cluster. The matrix-computer-cluster may include a matrix formation of x, y and z coordinates. Methods may encapsulate a first device in a first quantum case. Methods may receive a data element at the first device. Methods may intercept the data element at the first case. Methods may generate a random number sequence at a first quantum random number generator included in the first case. The random number sequence may identify a set of x, y and z coordinates. Methods may determine a second device located within the matrix-computer-cluster that corresponds to the identified set of x, y and z coordinates. Methods may include transmitting the data element to second device, and storing the data element at the second device.

Abstract: Embodiments of the present disclosure provide a wireless charging system, a wireless charging device, and a wireless power receiving device, and relate to the field of wireless charging. The system includes a wireless charging device and a wireless power receiving device. The wireless charging device includes a wireless charging module, a first function module, and a first communication module, and the wireless charging module includes a radio frequency transmitting antenna; the wireless power receiving device includes a wireless power receiving module, a second function module and a second communication module; the wireless charging module is configured to supply power to the wireless power receiving device through the radio frequency transmitting antenna; and the first function module and the second function module communicate with each other through the first communication module and the second communication module.

Abstract: An optimization device includes: a memory; and a processor configured to: calculate, as bit operations, when any bit in a bit string representing a state of an Ising model is inverted, an energy change value of the Ising model based on a coefficient indicating magnitude of an interaction between an own bit and the inverted bit in the bit string; output a first signal indicating inversion availability of the own bit according to the energy change value and a second signal indicating the energy change value; select the bit to be inverted in the bit string and the energy change value corresponding to the bit based on the first signal and the second signal; output a fourth signal indicating the selected energy change value; and calculate energy of the Ising model based on the energy change value indicated by the fourth signal.

Abstract: A coil device for a motor vehicle has a housing which has a receiving area, at least one secondary coil which is arranged in the receiving area for inductively transmitting electric energy in order to charge an energy storage unit of the motor vehicle, and at least one ferrite element which is arranged in the housing for conducting at least one magnetic field in order to inductively transmit the electric energy. The ferrite element has at least two ferrite regions that are at least partly mutually spaced by at least one through-opening which is arranged between the ferrite regions and in which a support structure is at least partly arranged that is made of a fiber composite material and has ferrite elements received in the fiber composite material, wherein opposing housing elements of the housing are supported against each other via said support structure.

Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.

Abstract: A wireless charging assembly includes a substrate and a charging emission trace on the substrate. The wireless charging assembly further includes a touch structure on a side, which is away from the charging emission trace, of the substrate. A preparation method of the wireless charging assembly, a terminal device and a wireless charging method for the terminal device are also provided.

Abstract: Biomedical implants in accordance with various embodiments of the invention can be implemented in many different ways. The implants can be configured to receive power and transmit data, both wirelessly and simultaneously. Such devices can be configured to receive power from an external source and transmit data, such as but not limited to recorded neural data and/or other biological data, to outside the body. In many cases, the data is transmitted to the device that delivers power to the implant. For example, the power and data transmission system can be implemented with a pair of transceivers. The implant transceiver can receive power wirelessly though an external transceiver while simultaneously transmitting data to the external transceiver. In several embodiments, both forward (power) and reverse (data) links use the same pair of inductive coils in the transceivers, one coil mounted in the implant and the other in the external unit.

Abstract: A dual stage power converter and a method for charging an energy storage device are presented. The dual stage power converter has a first stage and a second stage arranged in series. A first stage has a voltage divider circuit with a flying capacitor to convert an input voltage at an input of the dual stage power converter into a smaller, intermediate voltage at an intermediate node of the dual stage power converter. A second stage has a voltage regulator circuit to receive said intermediate voltage for regulating, using a feedback loop, an output voltage at an output of the dual stage power converter. The described dual stage power converter enables a reduction of the switching power losses in the voltage regulator circuit and a reduction of the resistive power losses within an external cable connecting the dual stage power converter with an external wall adapter.

Abstract: Disclosed herein is a wireless charging apparatus for preventing cancelation of magnetic fields generated between a plurality of adjacent transmission coils by placing a repeater on the plurality of transmission coils, the wireless charging apparatus including a plurality of transmission coils spaced the same distance apart from a reference point, and a repeater placed on the plurality of transmission coils to be overlapped with each of the plurality of transmission coils with respect to the reference point that is a center, wherein a coupling coefficient between each of the plurality of transmission coils and the repeater is higher than a coupling coefficient between the plurality of transmission coils.

Abstract: An electronic includes: a housing including a first plate, a second plate, and a side member; a display; a conductive coil parallel to the second plate and disposed between the display and the second plate; a wireless charging circuitry electrically connected to the conductive coil; and a processor operatively connected with the display and the wireless charging circuitry. The wireless charging circuitry receives a signal for wirelessly transferring power to an external electronic device from the processor, receives information about the external electronic device, receives a power control signal from the external electronic device via the conductive coil, applies a charging current of a first frequency to the conductive coil based at least in part on a request signal, increases a frequency of the charging current, compares the increased frequency with a first value, and adjusts a duty cycle of the charging current.

Abstract: A hardware monitor arranged to detect livelock in a hardware design for an integrated circuit. The hardware monitor includes monitor and detection logic configured to detect when a particular state has occurred in an instantiation of the hardware design; and assertion evaluation logic configured to periodically evaluate one or more assertions that assert a formal property related to reoccurrence of the particular state in the instantiation of the hardware design to detect whether the instantiation of the hardware design is in a livelock comprising the predetermined state. The hardware monitor may be used by a formal verification tool to exhaustively verify that the instantiation of the hardware design cannot enter a livelock comprising the predetermined state.