Abstract: In one aspect, a transistor-level description of a circuit is accessed, where the circuit includes a plurality of transistors. A transistor-level circuit simulation of the circuit's response to an input stimulus is performed, based on the transistor-level description of the circuit. Activity levels for the transistors in the circuit are determined from the transistor-level circuit simulation. A graphical representation of the circuit is rendered. The graphical representation contains graphical elements that represent components of the circuit, and the graphical elements are visually coded according to the activity levels of the transistors in the corresponding components.

Abstract: A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.

Abstract: The present invention pertains to a method of verifying a design of an integrated circuit. The methods executes an iteration of simulation test cycle using a digital representation of the design. Next, the method obtains simulation results from the iteration of the simulation test cycle and calculates, during the simulation test cycle, a test coverage value associated with the simulation results of the iteration of the simulation test cycle. If the test coverage value is less than a target value, the method determines if the simulation test cycle fails to satisfies an iteration limiting metric. If the simulation test cycle satisfies the iteration limiting metric, the method, dynamically adjusts one or more simulation test cycle parameter during the simulation test cycle and iterates the simulation test cycle and recalculating the test coverage value until the test coverage value is at least the target value or the simulation test cycle fails to satisfy the iteration limiting metric.

Abstract: Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.

Abstract: A method for realizing an artificial neural network via an electronic integrated circuit (FPGA), wherein artificial neurons grouped into different interlinked layers for the artificial neural network, where a functional description is created for each neuron of the artificial neural network, taking into account a specifiable starting weighting, a synthesis is performed for each neuron based on the associated functional description with the associated specified starting weighting, a network list is determined as the synthesis result, in which at least a base element and a starting configuration belonging to the base element are stored for each neuron, a base element is formed as a lookup table (LUT) unit and an associated dynamic configuration cell, in which a current configuration for the LUT unit or the base element is stored, and where the network list is implemented as a starting configuration of the artificial neural network in the electronic integrated circuit.

Abstract: A method of manufacturing a semiconductor device includes reducing errors in a migration of a first netlist to a second netlist, the first netlist corresponding to a first semiconductor process technology (SPT), the second first netlist corresponding to a second SPT, the first and second netlists each representing a same circuit design, the reducing errors including: inspecting a timing constraint list corresponding to the second netlist for addition candidates; generating a first version of the second netlist having a first number of comparison points relative to a logic equivalence check (LEC) context, the first number of comparison points being based on the addition candidates; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.

Abstract: A power system adapted for supplying power in a high temperature environment is disclosed. The power system includes a rechargeable energy storage that is operable in a temperature range of between about seventy degrees Celsius and about two hundred and fifty degrees Celsius coupled to a circuit for at least one of supplying power from the energy storage and charging the energy storage; wherein the energy storage is configured to store between about one one hundredth (0.01) of a joule and about one hundred megajoules of energy, and to provide peak power of between about one one hundredth (0.01) of a watt and about one hundred megawatts, for at least two charge-discharge cycles. Methods of use and fabrication are provided. Embodiments of additional features of the power supply are included.

Abstract: The present invention relates to a method for generating a security identifier for a control unit (10) of a battery system (100), comprising the steps of supplying an operation voltage to the control unit (10), outputting calibration data from a non-volatile memory element (15a) of the control unit (10), and generating a security identifier from the calibration data using a security algorithm. Therein, the calibration data is based on at least one testing process performed on the control unit (10) and is required for a faultless operation of the control unit (10). Further, according to a method for generating an activation key for a control unit (10) of a battery system (100) an activation key is generated based on such security identifier and output from the control unit (10). The invention further relates to an activation method for such control unit (10), wherein a control unit (10) is activated in response to the validation of such security identifier.

Abstract: A solar wireless collector beacon (data hub) and associated method stores source data, received wirelessly from a data source, in a data buffer of the data hub. Sensor data is read from one or more onboard sensors of the data hub and stored as structural and/or environmental data in the data buffer. The environmental data is processed to determine an operating status of a vehicle being used with the data hub and an energy harvester of the vehicle is controlled to harvest energy from the vehicle based on the operating status. One or more of the operating status, the source data, and the environmental data is wirelessly transmitted from the data hub to an external device.

Abstract: A method for vegetation restoration or rehabilitation of simulating a natural ecosystem based on machine learning (ML) includes: acquiring historical growth environment data of a vegetation community; extracting a site condition feature and a growth condition feature of each vegetation species; restoring and rehabilitating a vegetation community structure selection model; and selecting, based on the vegetation community structure selection model, an optimal vegetation species according to current growth environment data of the vegetation community, and restoring and rehabilitating a vegetation community simulating a natural ecosystem. The method comprehensively considers various factors affecting vegetation restoration based on the site condition and the growth condition.

Abstract: Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns.

Abstract: Multi-cell battery management devices, systems, and methods are disclosed herein. A multi-cell battery management device comprises a battery pack including a power output terminal and a plurality of battery cells each having a positive and a negative terminal and connected in series fashion. Each of the plurality of battery cells includes: i) a cell control processor to monitor cell voltage, cell current, cell temperature, and cell fuse status; ii) a programmable shunt controlled by the cell control processor that varies the internal resistance of each of the cells; and iii) a data communications circuit connected to the cell control processor and to the positive and negative terminals of each cell, the communications circuit enabling data communication over the battery cell positive and negative output terminals, and wherein the cell control processor responds to commands received via the data communications circuit to vary the operating state of the programmable shunt.

Abstract: The present disclosure provides a method and an apparatus for testing a semiconductor device. The method includes providing an active area in an integrated circuit design layout; grouping the active area into a first region and a second region; calculating a first self-heating temperature of the first region of the active area; calculating a second self-heating temperature of the second region of the active area; and determining an Electromigration (EM) evaluation based on the first self-heating temperature and the second self-heating temperature.

Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with point-to-point connections between modules. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. For example, type parameterization may be used to generate point-to-point connections in a flexible manner. For example, a point-to-point connection between the source module and the sink module that includes one or more named wires specified by bundle type may be automatically generated based on using the bundle type as a type parameterization input. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

Abstract: A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

Abstract: A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

Abstract: A learning device for performing a machine learning based on a learning model using data input to an input layer, includes: a calculation part configured to calculate a predetermined number of features, in which simulation data as a result of simulating semiconductor manufacturing processes by setting environmental information inside a process vessel in which the semiconductor manufacturing processes are performed and using a predetermined component provided in the process vessel as a variable, and XY coordinates parallel to a plane of a wafer are associated with each other; and an input part configured to input the calculated predetermined number of features to the input layer.

Abstract: The system includes a rail mountable to a wall, such as a wall along a hallway in a medical care environment. A cart movable along a floor adjacent to the wall is fitted with an anchor. The anchor is located at the rail, the anchor configured so that it releasably engages the rail, so that the cart can be secured to the rail when not in use. In at least some embodiments, a power source is located within the rail and a power coupler is provided on the cart which is adjacent to the power source in the rail and electrically coupled to the power source, for transmission of power from the power source in the rail to the cart, when of the anchor on the cart is attached to the rail. Thus, the cart is both anchored and recharged simultaneously in such embodiments.

Abstract: Provided is an energy storage apparatus capable of appropriately controlling use of a silicon material in normal times and achieving long life, and a method of using the energy storage apparatus. One aspect of the present invention is an energy storage apparatus that includes an energy storage device and a measuring section for measuring an internal pressure change rate of the energy storage device, the energy storage device having a negative electrode that contains a carbon material and a silicon material. Another aspect of the present invention is a method of using the energy storage apparatus that includes performing discharge while the internal pressure change rate of the energy storage device is measured.

Abstract: The present invention concerns a method and a tool for designing and validating a data flow system comprising a set of software and/or hardware actors (ai, aj) interconnected with each other by unidirectional communication channels (ci, cj), the tool comprising: —a modelling interface (11) configured to generate an instance of the system by specifying, in a formal manner, a real-time and reconfigurable data flow, the reconfiguration of the data flow being carried out dynamically by propagating reconfiguration data from one actor to another through the communication channels, —an analysis module (13) configured to prove a predetermined set of behavioral properties of the system by means of a static analysis of the instance, —a refinement interface (15) designed to allocate resources to the instance, thus establishing a configured instance, the allocation of resources being carried out in such a way that an implementation of the system complies with the configured instance, and —a conformity test module (17) co