Abstract: A power semiconductor module includes: an electrically insulative frame having opposite first and second mounting sides, and a border that defines a periphery of the electrically insulative frame; a first substrate seated in the electrically insulative frame; a plurality of power semiconductor dies attached to the first substrate; a plurality of signal pins attached to the first substrate and electrically connected to the power semiconductor dies; a plurality of busbars attached to the first substrate and extending through the border of the electrically insulative frame; a plurality of fixing positions at the first mounting side of the electrically insulative frame; and a plurality of electrically insulative protrusions jutting out from the second mounting side of the electrically insulative frame, wherein the protrusions are vertically aligned with the fixing positions.

Abstract: A micromechanical component for a capacitive pressure sensor device, including a diaphragm that is stretched with the aid of a frame structure in such a way that a cantilevered area of the diaphragm spans a framed partial surface, and including a reinforcement structure that is formed at the cantilevered area. A first spatial direction oriented in parallel to the framed partial surface is definable in which the cantilevered area has a minimal extension, and a second spatial direction oriented in parallel to the framed partial surface and oriented perpendicularly with respect to the first spatial direction is definable in which the cantilevered area has a greater extension. The reinforcement structure is present at a first distance from the frame structure in the first spatial direction, and at a second distance in the second spatial direction, the second distance being greater than the first distance.

Abstract: The disclosure discloses a layout structure of an eFuse unit, comprising pad, link, and shield, wherein: a pad is respectively disposed on both ends of the link in a length direction; the shield and the link are at the same metal layer; the shield comprises a plurality of independent metal wires; the plurality of independent metal wires are arranged on both sides of the link; the length of each independent metal wire is greater than the width thereof; and a length direction of each independent metal wire is perpendicular to the length direction of the link. The disclosure not only forms a barrier protection layer for preventing burst metal spraying from affecting other circuits, but also can prevent spayed metal from reflecting back and connecting to a broken link, so as to improve the programming reliability of the eFuse unit.

Abstract: A stacked via structure including a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer and a second conductive via is provided. The first dielectric layer includes a first via opening. The first conductive via is in the first via opening. A first level height offset is between a top surface of the first conductive via and a top surface of the first dielectric layer. The first redistribution wiring covers the top surface of the first conductive via and the top surface of the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer and the first redistribution wiring. The second dielectric layer includes a second via opening. The second conductive via is in the second via opening. The second conductive via is electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer.

Abstract: A semiconductor device including a semiconductor structure including a first semiconductor layer, a second semiconductor layer, and an active layer; a first electrode provided on a first surface of the first semiconductor layer; a second electrode provided on a first surface of the second semiconductor layer, the active layer being provided between the first surface of the first semiconductor layer and a second surface of the second semiconductor layer that is opposite to the first surface of the second semiconductor layer; a first insulation layer provided on the first surface of the first semiconductor layer, the first surface of the second semiconductor layer, and a side surface of the active layer; a first cover electrode provided on the first electrode; a second cover electrode provided on the second electrode, a second insulation layer provided on the first cover electrode, the second cover electrode, and the first insulation layer, wherein: the second insulation layer includes a first opening over the

Abstract: A method provides a circuit carrier arrangement that includes: a cooling plate (1) which has spacer and fastening elements (3) for connection to a printed circuit board (2) in a spaced-apart manner; a printed circuit board (2) which has bores (4) for receiving spring element sleeves (9); at least one power semiconductor component (10) which is connected by a soldered connection to the printed circuit board (2) and fastening elements (3) in the state in which it is fitted with the cooling plate (1) by means of plug-in connections (11) of spring-action configuration; and at least one spring element (5) having at least two spring element sleeves (9) between which a web (6) that is connected to the spring element sleeves (9) extends, and supporting elements (7) arranged on either side of said web and at least one spring plate (8) being arranged on said web.

Abstract: A bonded structure is disclosed. The bonded structure includes a first element and a second element that is bonded to the first element along a bonding interface. The bonding interface has an elongate conductive interface feature and a nonconductive interface feature. The bonded structure also includes an integrated device that is coupled to or formed with the first element or the second element. The elongate conductive interface feature has a recess through a portion of a thickness of the elongate conductive interface feature. A portion of the nonconductive interface feature is disposed in the recess.

Abstract: An electronic device is provided and includes a first electrode, a second electrode and a photoelectric conversion layer sandwiched between the first electrode and the second electrode, the first electrode including an amorphous oxide including a quaternary compound including one or more of indium, gallium and aluminum and further including zinc and oxygen, the first electrode having a laminated structure including a first B layer and a first A layer from a photoelectric conversion layer side, and a work function value of the first A layer of the first electrode being lower than a work function of the first B layer of the first electrode.

Abstract: Systems for physical unclonable function (“PUF”) generation, PUF devices, and methods for manufacturing PUF devices. In one implementation, the system includes a plurality of PUF devices and an electronic controller. Each of the plurality of PUF devices include a first electrochemically-inactive electrode, a second electrochemically-inactive electrode, and a layer of silicon suboxide. The layer of silicon suboxide is positioned directly between the first electrochemically-inactive electrode and the second electrochemically-inactive electrode. The electronic controller is communicably coupled to the plurality of PUF devices. The electronic controller is configured to read binary values associated with the plurality of PUF devices.

Abstract: An interlayer dielectric layer covers an electric fuse element. A resistance layer made of silicon metal is arranged on the interlayer dielectric layer and directly above the electric fuse element.

Abstract: A semiconductor package includes; a lower semiconductor chip mounted on a lower package substrate, an interposer on the lower package substrate and including an opening, connection terminals spaced apart from and at least partially surrounding the lower semiconductor chip and extending between the lower package substrate and the interposer, a first molding member including a first material and covering at least a portion of a top surface of the lower semiconductor chip and at least portions of edge surfaces of the lower semiconductor chip, wherein the first molding member includes a protrusion that extends upward from the opening to cover at least portions of a top surface of the interposer proximate to the opening, and a second molding member including a second material, at least partially surrounding the first molding member, and covering side surfaces of the first molding member and the connection terminals, wherein the first material has thermal conductivity greater than the second material.

Abstract: Provided is a semiconductor module, including: a semiconductor chip; a circuit board on which the semiconductor chip is mounted; a sealing resin including epoxy resin for sealing the semiconductor chip and the circuit board; and a reinforcing material, with a higher Young's modulus than the sealing resin, provided in close contact with the sealing resin above at least a part of the sealing resin. The semiconductor module includes a resin case for enclosing spaces for housing the semiconductor chip, wherein the sealing resin may be provided inside the resin case.

Abstract: A method for manufacturing a light emitting display device, includes preparing a substrate having an active area and edge areas around the active area, forming a first electrode in each of a plurality of subpixels in the active area, forming a first common layer configured to cover an entirety of the active area and to have a first process margin in the edge areas outside the active area, forming a conductivity improvement layer on the first common layer in the edge areas, forming a light emitting layer in each of the subpixels, forming a second common layer having a large size than a size of the active area, on the light emitting layer, and forming a second electrode having a second process margin in the edge areas to cover at least the first common layer, on the second common layer.

Abstract: An object of the present disclosure is to provide a technique capable of relaxing the stress to be applied around the attachment hole of the resin case at the time of fixing the resin case accommodating the semiconductor element to the heat dissipation component with a bolt. A semiconductor device includes a base plate, a heat dissipation component, and a resin case. In a state where the resin case is disposed on the heat dissipation component via the base plate, the resin case is attached to the heat dissipation component with a bolt. The resin case has a recess portion, an attachment hole formed below the recess portion, and at least one groove formed between a wall portion on an inner peripheral side forming the recess portion and the attachment hole. One end of the at least one groove reaches an outer peripheral end of the resin case.

Abstract: A hermetic package of the present invention includes a package base and a glass cover hermetically sealed with each other via a sealing material layer, wherein the package base includes a base part and a frame part formed on the base part, wherein the package base has an internal device housed within the frame part, wherein the sealing material layer is arranged between a top of the frame part of the package base and the glass cover, and wherein an end portion of the sealing material layer protrudes laterally in an arc shape in sectional view.

Abstract: An image sensor having pixels that include two patterned semiconductor layers. The top patterned semiconductor layer contains the photoelectric elements of pixels having substantially 100% fill-factor. The bottom patterned semiconductor layer contains transistors for detecting, resetting, amplifying and transmitting signals charges received from the photoelectric elements. The top and bottom patterned semiconductor layers may be separated from each other by an interlayer insulating layer that may include metal interconnections for conducting signals between devices formed in the patterned semiconductor layers and from external devices.

Abstract: A semiconductor memory device includes a substrate, a plurality of first conductive layers, a second conductive layer disposed at a position farther from or a position closer to the substrate than the plurality of first conductive layers, a first semiconductor column, a first electric charge accumulating film, a first wiring disposed at a position farther from or a position closer to the substrate than the plurality of first conductive layers and the second conductive layer, a first contact that is disposed between one end of the second conductive layer and the first semiconductor column and is electrically connected to the second conductive layer and the first wiring, and a second contact that is disposed between another end of the second conductive layer and the first semiconductor column and is electrically connected to the second conductive layer and the first wiring.

Abstract: A memory cell comprises channel material, charge-passage material, programmable material, a charge-blocking region, and a control gate. The programmable material comprises at least two regions comprising SiNx having a region comprising SiOy therebetween, where “x” is 0.5 to 3.0 and “y” is 1.0 to 3.0. Methods are disclosed.

Abstract: Heterostructures containing one or more sheets of positive charge, or alternately stacked AlGaN barriers and AlGaN wells with specified thickness are provided. Also provided are multiple quantum well structures and p-type contacts. The heterostructures, the multiple quantum well structures and the p-type contacts can be used in light emitting devices and photodetectors.

Abstract: A mechanism is provided to secure integrated circuit devices that combines a high degree of security with a low overhead, both in area and cost, thereby making it appropriate for smaller, cheaper integrated circuits. A determination is made whether a device die is on a wafer or if the device die is incorporated into a package. Only if the device die is incorporated in a package can the functional logic of device die be activated, and then only if a challenge-response query is satisfied. In some embodiments, a random number generator is used during wafer testing to form a pair of numbers, along with a die identifier, that is unique for each device die. A final test is then performed in which the device die can be activated if the device die is incorporated in a package, and the die identifier—random number pair is authenticated.