Abstract: An optoelectronic component and a lighting apparatus are disclosed. In an embodiment an optoelectronic component includes a carrier having an upper side and an underside opposite the upper side, an optoelectronic semiconductor chip arranged on the upper side of the carrier, the semiconductor chip configured to emit primary radiation during operation via one or more sides. The component further includes a first conversion layer having an inorganic phosphor on the semiconductor chip, the first conversion layer covering at least all radiation-emitting sides of the semiconductor chip not facing the carrier and a solid body in which an organic phosphor is distributed, wherein the solid body is arranged and fastened on the carrier and is at least in indirect contact with the carrier, and wherein the solid body is spaced from the radiation-emitting sides of the semiconductor chip at least by the first conversion layer and/or by the carrier.

Abstract: There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.

Abstract: According to one aspect of the present disclosure, a semiconductor module includes a semiconductor chip having a first electrode, a second electrode, and a control electrode to receive a control signal that controls a current flowing between the first electrode and the second electrode, a package having an upper surface, a back surface that is an opposite surface of the upper surface, and a plurality of side surfaces provided between the upper surface and the back surface, the package containing the semiconductor chip, a first terminal provided to the package and being electrically connected to the first electrode, a second terminal provided to the package and being electrically connected to the second electrode and a control terminal electrically connected to the control electrode and being provided on all of the plurality of side surfaces of the package so as to surround the package.

Abstract: An image sensor having pixels that include two patterned semiconductor layers. The top patterned semiconductor layer contains the photoelectric elements of pixels having substantially 100% fill-factor. The bottom patterned semiconductor layer contains transistors for detecting, resetting, amplifying and transmitting signals charges received from the photoelectric elements. The top and bottom patterned semiconductor layers may be separated from each other by an interlayer insulating layer that may include metal interconnections for conducting signals between devices formed in the patterned semiconductor layers and from external devices.

Abstract: A method for manufacturing an integrated circuit package includes depositing a first layer of metal at a location of a first metal post that is for connecting an IC die to an external circuit. The method also includes depositing a second layer of metal at the location of the first metal post, and a first layer of metal at a location of a second metal post that is for connecting the IC die to an external circuit.

Abstract: An imaging device is provided. The imaging device includes a semiconductor substrate; a first electrode disposed above the semiconductor substrate; a second electrode disposed above the first electrode; and a photoelectric conversion layer disposed between the first electrode and the second electrode, wherein a difference between a work function value of the first electrode and a work function value of the second electrode is 0.4 eV or more, and wherein the first electrode has a sheet resistance value of 3×10 ?/? to 1×103?/?.

Abstract: A semiconductor package device includes a circuit layer, a first set of stacked components, a first conductive wire, a space and an electronic component. The first set of stacked components is disposed on the circuit layer. The first conductive wire electrically connects the first set of stacked components. The space is defined between the first set of stacked components and the circuit layer. The space accommodates the first conductive wire. The electronic component is disposed in the space.

Abstract: A device includes a substrate, a first doping portion, a second doping portion, a channel, a semiconductor film, a high-k layer, and a gate. The first doping portion and the second doping portion are over the substrate. The channel is over the substrate and between the first doping portion and the second doping portion. The semiconductor film is around the channel. The high-k layer is around the semiconductor film. The gate is over the high-k layer.

Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.

Abstract: An micro electro mechanical sensor comprising: a substrate; and a sensor element movably mounted to a first side of said substrate; wherein a second side of said substrate has a pattern formed in relief thereon. The pattern formed in relief on the second side of the substrate provides a reduced surface area for contact with the die bond layer. The reduced surface area reduces the amount of stress that is transmitted from the die bond layer to the substrate (and hence reduces the amount of transmitted stress reaching the MEMS sensor element). Because the substrate relief pattern provides a certain amount of stress decoupling, the die bond layer does not need to decouple the stress to the same extent as in previous designs. Therefore a thinner die bond layer can be used, which in turn allows the whole package to be slightly thinner.

Abstract: There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.

Abstract: Heterostructures containing one or more sheets of positive charge, or alternately stacked AlGaN barriers and AlGaN wells with specified thickness are provided. Also provided are multiple quantum well structures and p-type contacts. The heterostructures, the multiple quantum well structures and the p-type contacts can be used in light emitting devices and photodetectors.

Abstract: A display device includes: a flexible substrate; a plurality of conductive lines on the flexible substrate; a thin film transistor connected to the plurality of conductive lines; and an organic light emitting element connected to the thin film transistor. As a curvature of an area of the flexible substrate increases, a width or a thickness of each of the conductive lines increases.

Abstract: A system in package and method for making a system in package. A plurality of passive devices are coupled to an interposer. A molding compound envelopes the plurality of passive devices and defines a platform having a substantially planar surface. The interposer is coupled to a substrate. A plurality of integrated circuit dies are coupled in a stack to the planar surface.

Abstract: An image sensor having pixels that include two patterned semiconductor layers. The top patterned semiconductor layer contains the photoelectric elements of pixels having substantially 100% fill-factor. The bottom patterned semiconductor layer contains transistors for detecting, resetting, amplifying and transmitting signals charges received from the photoelectric elements. The top and bottom patterned semiconductor layers may be separated from each other by an interlayer insulating layer that may include metal interconnections for conducting signals between devices formed in the patterned semiconductor layers and from external devices.

Abstract: Embodiments of the invention address several issues and problems associated with etching of dielectric materials for BEOL applications. According to one embodiment, the method includes providing a patterned substrate containing a dielectric material, exposing the substrate to a gas phase plasma to functionalize a surface of the dielectric material, exposing the substrate to a silanizing reagent that reacts with the functionalized surface of the dielectric material to form a dielectric film, and sequentially repeating the exposing steps at least once to increase a thickness of the dielectric film. According to one embodiment, the dielectric material may be a porous low-k material, and the dielectric film seals the pores on a surface of the porous low-k material.

Abstract: Implementations of semiconductor packages may include: a wafer having a first side and a second side, a solder pad coupled to the first side of the wafer, a through silicon via (TSV) extending from the second side of the wafer to the solder pad a metal layer around the walls of the TSV, and a low melting temperature solder in the TSV. The low melting temperature solder may also be coupled to the metal layer. The low melting temperature solder may couple to the solder pad through an opening in a base layer metal of the solder pad.

Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.

Abstract: A structure includes a metal layer and a plurality of interconnected unit cells forming a lattice contained at least partly within the metal layer, including at least a first unit cell formed of first interconnected graphene tubes, and a second unit cell formed of second interconnected graphene tubes, wherein the metal layer protrudes through holes within the lattice.

Abstract: In an example, a method may include removing a material from a structure to form an opening in the structure, exposing a residue, resulting from removing the material, to an alcohol gas to form a volatile compound, and removing the volatile compound by vaporization. The structure may be used in semiconductor devices, such as memory devices.