Abstract: Heterostructures containing one or more sheets of positive charge, or alternately stacked AlGaN barriers and AlGaN wells with specified thickness are provided. Also provided are multiple quantum well structures and p-type contacts. The heterostructures, the multiple quantum well structures and the p-type contacts can be used in light emitting devices and photodetectors.

Abstract: A mechanism is provided to secure integrated circuit devices that combines a high degree of security with a low overhead, both in area and cost, thereby making it appropriate for smaller, cheaper integrated circuits. A determination is made whether a device die is on a wafer or if the device die is incorporated into a package. Only if the device die is incorporated in a package can the functional logic of device die be activated, and then only if a challenge-response query is satisfied. In some embodiments, a random number generator is used during wafer testing to form a pair of numbers, along with a die identifier, that is unique for each device die. A final test is then performed in which the device die can be activated if the device die is incorporated in a package, and the die identifier—random number pair is authenticated.

Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

Abstract: The present disclosure relates to a method for preparing an electrical fuse (e-fuse) device. The method includes forming a mask layer over a semiconductor substrate, and etching the semiconductor substrate by using the mask layer as a mask to form a fuse link over a semiconductor base. The method also includes epitaxially growing a first bottom anode/cathode region and a second bottom anode/cathode region over the semiconductor base and adjacent to a bottom portion of the fuse link. The fuse link is between the first bottom anode/cathode region and the second anode/cathode region. The method further includes epitaxially growing a top anode/cathode region to replace the mask layer.

Abstract: In an example, a method may include removing a material from a structure to form an opening in the structure, exposing a residue, resulting from removing the material, to an alcohol gas to form a volatile compound, and removing the volatile compound by vaporization. The structure may be used in semiconductor devices, such as memory devices.

Abstract: A power semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type and a well region of a second conductivity type, a plurality of gate trenches including respective gate insulating layers and gate electrodes therein extending into the drift region, respective shielding patterns of the second conductivity type in respective portions of the drift region adjacent the gate trenches, and respective conduction enhancing regions of the first conductivity type in the respective portions of the drift region. The drift region comprises a first concentration of dopants of the first conductivity type, and the respective conduction enhancing regions comprise a second concentration of the dopants of the first conductivity type that is higher than the first concentration. Related devices and fabrication methods are also discussed.

Abstract: Embodiments include a microelectronic device package structure having a first die on the substrate. One or more additional dice are on the first die, and a thermal electric cooler (TEC) is on the first die adjacent at least one of the one or more additional dice. A dummy die is on the TEC, wherein the dummy die is thermally coupled to the first die.

Abstract: A power module is disclosed. A power module according to an embodiment of the present disclosure may include a first substrate and a second substrate spaced apart from each other, an electronic device unit provided on at least either one of the first and second substrates, and a lead frame unit provided between the first and second substrates. One side of the lead frame unit may be connected to an external circuit, and the other side thereof may be configured to electrically connect the first and second substrates. Accordingly, the lead frame unit may perform a function of electrically connecting the first and second substrates instead of a via spacer in the related art.

Abstract: Techniques are disclosed for providing cladded metal interconnects. Given an interconnect trench, a barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first layer of a bilayer adhesion liner is selectively deposited on the barrier layer, and a second layer of the bilayer adhesion liner is selectively deposited on the first layer. An interconnect metal is deposited into the trench above the bilayer adhesion liner. Any excess interconnect metal is recessed to get the top surface of the interconnect metal to a proper plane. Recessing the excess interconnect metal may include recessing previously deposited excess adhesion liner and barrier layer materials. The exposed top surface of the interconnect metal in the trench is then capped with the bilayer adhesion liner materials to provide a cladded metal interconnect core. In some embodiments, the adhesion liner is a single layer adhesion liner.

Abstract: In one embodiment, a semiconductor device includes a stacked film including electrode layers and insulating layers that are alternately stacked in a first direction. The device further includes a first insulator, a charge storage layer, a second insulator and a semiconductor layer that are provided in the stacked film. The device further includes a third insulator provided between an electrode layer and an insulating layer and between the electrode layer and the first insulator, and including aluminum oxide having an ? crystal phase.

Abstract: A circuit carrier arrangement includes: a cooling plate (1) which has spacer and fastening elements (3) for connection to a printed circuit board (2) in a spaced-apart manner; a printed circuit board (2) which has bores (4) for receiving spring element sleeves (9); at least one power semiconductor component (10) which is connected by a soldered connection to the printed circuit board (2) and fastening elements (3) in the state in which it is fitted with the cooling plate (1) by means of plug-in connections (11) of spring-action configuration; and at least one spring element (5) having at least two spring element sleeves (9) between which a web (6) that is connected to the spring element sleeves (9) extends, and supporting elements (7) arranged on either side of said web and at least one spring plate (8) being arranged on said web.

Abstract: A MRAM structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with storage units on corresponding active areas, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.

Abstract: Provided is a semiconductor device comprising a semiconductor substrate containing oxygen. An oxygen concentration distribution in a depth direction of the semiconductor substrate has a high oxygen concentration part where an oxygen concentration is higher on a further upper surface-side than a center in the depth direction of the semiconductor substrate than in a lower surface of the semiconductor substrate. The high oxygen concentration part may have a concentration peak in the oxygen concentration distribution. A crystal defect density distribution in the depth direction of the semiconductor substrate has an upper surface-side density peak on the upper surface-side of the semiconductor substrate, and the upper surface-side density peak may be arranged within a depth range in which the oxygen concentration is equal to or greater than 50% of a peak value of the concentration peak.

Abstract: An imaging device includes a first chip (72). The first chip includes first and second pixels including respective first and second photoelectric conversion regions (PD) that convert incident light into electric charge. The first chip includes a first connection region for bonding the first chip to a second chip (73) and including a first connection portion (702, 702d) overlapped with the first photoelectric conversion region in a plan view, and a second connection portion overlapped with the second photoelectric conversion region in the plan view. The first photoelectric region receives incident light of a first wavelength, and the second photoelectric conversion region receives incident light of a second wavelength that is greater than the first wavelength. The first connection portion overlaps an area of the first photoelectric conversion region that is larger than an area of the second photoelectric conversion region overlapped by the second connection portion.

Abstract: A semiconductor structure includes a resistance tunable fuse stack structure. A fabrication method for forming the same includes forming on a substrate layer a first fuse conductive layer, directly on, and contacting a top surface of, the substrate layer, followed by forming a first inter-layer dielectric (ILD) layer, directly on, and contacting a top surface of, the first fuse conductive layer. The method forms a second fuse conductive layer, directly on, and contacting a top surface of, the first ILD layer, followed by forming a second ILD layer, directly on, and contacting a top surface of, the second fuse conductive layer, the layers are interleaved in a stack forming a fuse stack structure. First and second fuse contacts are formed in the fuse stack structure vertically extending through the layers and contacting the first and second fuse conductive layers.

Abstract: A semiconductor device may include a first semiconductor substrate having a first surface and a second surface opposite to each other, a first circuit layer provided on the first surface of the first semiconductor substrate, a connection pad provided on the second surface of the first semiconductor substrate, and a first penetration via and a second penetration via penetrating the first semiconductor substrate and at least a portion of the first circuit layer. The first penetration via and the second penetration via may be provided in a first penetration hole and a second penetration hole, respectively. Each of the first and second penetration holes may include a first portion, a second portion, and a third portion. A width of the first portion of the first penetration hole may be smaller than a width of the first portion of the second penetration hole.

Abstract: The present disclosure provides a semiconductor device capable of reducing wiring resistance by using a stripe wire. The semiconductor device includes: a source pad electrode formed on a second interlayer insulating layer; a plurality of source extraction electrodes extracted in a first direction from the source pad electrode; a drain pad electrode formed on the second interlayer insulating layer; and a plurality of drain extraction electrodes extracted in the first direction from the drain pad electrode. The source pad electrode and the plurality of source extraction electrodes are electrically connected to a plurality of source wires of stripe wire covered by the second interlayer insulating layer. The drain pad electrode and the plurality of drain extraction electrodes are electrically connected to a plurality of drain wires of the stripe wire. The plurality of drain extraction electrodes are engaged with the plurality of source extraction electrodes.

Abstract: A semiconductor element includes a main body and an obverse face electrode. The main body includes an obverse face that faces in a thickness direction. The obverse face electrode is electrically connected to the main body. The obverse face electrode includes a first section and a plurality of second sections. The first section is provided on the obverse face. The plurality of second sections are in contact with the first section, and spaced apart from each other in a direction perpendicular to the thickness direction. A total area of the plurality of second sections is smaller than an area of the first section including portions overlapping with the plurality of second sections, in a view along the thickness direction.

Abstract: Provided is a display device including an organic insulating layer; a pixel electrode on the organic insulating layer; a pixel defining layer configured to cover an edge of the pixel electrode, having an opening corresponding to the pixel electrode, the pixel defining layer including a first layer including an inorganic insulating material and a second layer having less light transmittance in a first wavelength band than the first layer; an intermediate layer on a portion of the pixel electrode exposed via the opening, and including an emission layer; and an opposite electrode on the intermediate layer.

Abstract: A semiconductor device includes a metal plate; a sidewall member surrounding a periphery of a space above the metal plate; a circuit board provided on the metal plate; a semiconductor chip provided on the circuit board; a first wire connecting the semiconductor chip and an interconnect part of the circuit board; a first resin member covering a bonding portion between the semiconductor chip and the first wire; and a second resin member provided in the space, the second resin member covering an upper surface of the metal plate, the circuit board, the first resin member, and the first wire. A Young's modulus of the first resin member is greater than a Young's modulus of the second resin member. A volume of the second resin member is greater than a volume of the first resin member.